Programmable non-integer fractional divider
AssigneeInternational Buisness Machines Corporation
InventorsFrancis Bredin, Bertrand Gabillard, Francois Auguste Roger Meunier
Life of this patent
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Abstract
A non-integer fractional divider divides a reference clock signal having period P by a non-integer ratio K. The divider includes multiplexers to receive a plurality N of clock signals wherein each clock signal is equally phase shifted by a P/N delay. Incrementers coupled to the multiplexers select first and second clock signals between the N clock signals. Such that the phase shift delay between the two selected clock signals is representative of the non-integer value of K. The selected clock signals are combined to output a divided clock signal. The enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal.
Claims27
A non-integer fractional divider for dividing a clock signal (Fvco) of period (P) by a non-integer ratio (K), comprising:
- means (301,304) for receiving a plurality (N) of clock signals (Fvco_0 to Fvco_(N−1)), each clock signal having a period of (P) and being equally phase shifted by a (P/N) delay one over the other;
- means (303,306) coupled to the receiving means for selecting a first and a second clock signals between the plurality (N) of clock signals (Fvco_0 to Fvco_(N−1));
- means (302,305,307,308) responsive to the receiving means for combining the first and the second selected clock signals and for outputting a divided clock signal (Fvco/K), wherein the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio (K) and an enabling time of each selected clock signal is respectively representative of a duration of a low level and a high level of the divided clock signal, the duration of the low level and the duration of the high level being adjustable based at least in part on an adjustable decomposition of the non-integer ratio (K) into a sum (K0+K1).
A method for dividing by a non-integer ratio (K) a clock signal (Fvco) having a period ‘P’, comprising the steps of:
- receiving a plurality (N) of clock signals (Fvco_0 to Fvco_(N−1)), each clock signal having a period of ‘P’ and being equally phase shifted by a ‘P/N’ delay one over the other;
- selecting a first and a second clock signals between the plurality (N) of clock signals (Fvco_0 to Fvco_(N−1));
- combining the first and the second selected clock signals to output a divided clock signal (Fvco/K), wherein the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio (K) and an enabling time of each selected clock signal is respectively representative of a duration of a low level and a high level of the divided clock signal, the duration of the low level and the duration of the high level being adjustable based at least in part on an adjustable decomposition of the non-integer ratio (K) into a sum (K0+K1).
Dependencies are inferred from the claim text.