Method and apparatus for scan design using a formal verification-based process
AssigneeIntel Corporation
InventorsJoel T. Yuen, Kailasnath S. Maneparambil, Puneet Singh
Life of this patent
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Abstract
A scan cell design approach includes removing a formal verification property associated with a scan cell from a set of formal verification properties to create a reduced set of formal verification properties. A formal verification assumption verification process is then performed on a schematic using assumptions generated from the reduced set of formal verification properties. An output of the assumption verification process indicates whether there is a potential contention site at logic coupled to the output of the scan cell.
Claims20
A method comprising:
- removing a formal verification property associated with a scan cell from a set of formal verification properties to create a reduced set of formal verification properties;
- and
- performing an assumption verification process on a schematic using assumptions generated from the reduced set of formal verification properties, an output of the assumption verification process to indicate whether there is a potential contention site at logic coupled to the output of the scan cell.
A method comprising:
- applying a constraint to an automatic test pattern generation tool, the constraint being associated with a contention site that is revealed by removing a formal verification property associated with a functional output of a scan cell and performing an assumption verification process on a schematic with the formal verification property removed;
- and
- generating test vectors using the constraint.
A method comprising:
- removing a formal verification property associated with a functional output of a scan cell;
- performing an assumption verification process on an integrated circuit schematic with the formal verification property removed;
- determining whether logic coupled to the output of the scan cell includes a potential contention site based on a result of the assumption verification;
- and
- if the logic includes a potential contention site, determining whether contention is caused during a scan shift operation or when a vector is applied to the fan-out cone.
An article comprising a medium that stores instructions that cause a processor-based system to perform a method comprising:
- applying a constraint to an automatic test pattern generation tool, the constraint being associated with a contention site that is revealed by removing a formal verification property associated with a functional output of a scan cell and performing an assumption verification process with the formal verification property removed;
- and
- generating test vectors using the constraint.
An article comprising a medium that stores instructions that cause a processor-based system to perform a method comprising:
- removing a formal verification property associated with a scan cell functional output in an integrated circuit model;
- and
- performing an assumption verification process on a schematic of the integrated circuit including the scan cell, the assumption verification process to indicate whether there is a potential contention site at logic coupled to the output of the scan cell.
Dependencies are inferred from the claim text.