Acquisition system for a multi-channel relatively long record length digital storage oscilloscope

A long record length digital oscilloscope, comprising:

• a plurality of input terminals for receiving signals under test;
• an analog-to-digital converter having an input coupled to said input terminals for receiving said signals under test, and producing digital samples of said signals under test at an output;
• a trigger circuit having an input coupled to said input terminals for receiving said signals under test, and producing a trigger signal at an output in response to detection of a predetermined trigger event in one of said signals under test;
• a deep acquisition memory for storing said digital samples of said signals under test as a plurality of relatively long length data records that form a long length data record;
• a demultiplexer unit coupled between said analog-to-digital converter and said deep acquisition memory for receiving said digital samples and controlling the flow of said samples to said deep acquisition memory in response to said trigger signal;
• processor circuitry for examining said stored digital samples from said long length data record in a post acquisition mode of operation and producing an event detect signal in response to detection of a predetermined secondary event in said long length data record;
• and
• a system processor for causing a predetermined amount of said stored digital samples to be read from said deep acquisition memory for processing and display in response to said event detect signal;
• said predetermined amount of said stored digital samples being less than one of the relatively long length data records and being related in time to said event detect signal.

A digital storage oscilloscope, comprising:

• a plurality of input terminals for receiving signals under test;
• an analog-to-digital converter having an input coupled to said input terminals for receiving said signals under test, and producing digital samples of said signals under test at an output;
• a trigger circuit having an input coupled to said input terminals for receiving said signals under test, and producing a trigger signal at an output in response to detection of a predetermined trigger event in one of said signals under test;
• a deep acquisition memory for storing said digital samples of said signals under test as a plurality of relatively long data records that form a long length data record;
• a demultiplexer unit coupled between said analog-to-digital converter and said deep acquisition memory for receiving said digital samples and controlling the flow of said samples to said deep acquisition memory in response to said trigger signal;
• and
• a system processor for examining said stored digital samples from said long length data record in a post acquisition mode of operation for detecting a predetermined secondary event in said stored digital samples;
• said system processor causing a predetermined amount of said stored digital samples to be read from said deep acquisition memory for processing and display in response to said detection of said predetermined secondary event;
• said predetermined amount of said stored digital samples being less than one of said relatively long length data records and being related in time to said event detect signal.