System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system

A method for resetting a clock-skipping buffer comprising:

• in each of two clock domains, detecting each pulse of a corresponding clock signal which is substantially aligned with a corresponding reference clock pulse;
• receiving an asynchronous reset signal;
• generating an aligned reset signal in one of said clock domains, wherein said aligned reset signal is substantially aligned with one of said detected aligned pulses of said corresponding clock domain;
• delaying said aligned reset signal by an amount greater than a maximum skew between said clock signals in said clock domains;
• and
• in each of said two clock domains, asserting a synchronous reset signal.

In a microprocessor having a clock-skipping buffer for transferring data between a first clock domain and second clock domain, a circuit comprising:

• a first alignment unit, wherein said first alignment unit is configured to assert a first alignment signal indicative of the alignment of a pulse of a clock signal in said first clock domain with a pulse of a reference clock signal;
• a second alignment unit, wherein said second alignment unit is configured to assert a second alignment signal indicative of the alignment of a pulse of a clock signal in said second clock domain with said pulse of said reference clock signal;
• a synchronous reset unit coupled to said first and second alignment units and configured to receive an asynchronous reset signal and said first and second alignment signals, wherein said synchronous reset unit is configured to generate a first reset signal which is aligned with said first alignment signal and a second reset signal which is aligned with said second alignment signal;
• and
• a counter reset unit coupled to said synchronous reset unit to receive said first and second reset signals, wherein said counter reset unit is configured to reset a load counter based on said first reset signal and to reset an unload counter based on said second reset signal.