De-interleave circuit

A de-interleave circuit for recovering an original data arrangement from an interleaved data arrangement of a main signal, said interleaved data arrangement being formed in such a way to execute interleaving between slots having an identical frame slot number in a superframe direction, said de-interleave circuit, comprising:

• a de-interleave memory having a storage capacity of one superframe;
• and
• address data generating means for generating address data to specify a data read/write address location to said de-interleave memory,
• characterized in that said main signal stored in the memory address location specified by the address data generated by the address generating means is read and a following main signal to be interleaved and inputted is written in said address location,
• wherein said address data generating means generates address data A, where the number of main signals in 1 slot is designated as m, the depth of de-interleave is designated as n, a specific address number assigned to said de-interleave memory is designated as y, and address-data that specifies a data read/write address location is designated as A, and a modulo b is defined as being a remainder of a−αb (where each of a, α, and b is a natural number including 0),
• when (y≠n×m−1), A=y×n to the xth power modulo (n×m−1), and when (y=n×m−1), A=y,
• a value of address set number, which is the number of times data of up to address number y is repeatedly specified, is equal to an x that when y=1, A=1 in A=y×n to the xth power modulo (n×m−1) and
• when the value of y×n to the xth power is less than (n×m−1), A=(y×n to the xth power).