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US 6,748,027 B1Granted
CMI signal timing recovery
AssigneeIntel Corporation
InventorsNamik K. Kocaman, Michael W. Altmann
Life of this patent
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Abstract
An apparatus and method for recovering a clock signal from a Coded Marked Inversion (CMI) encoded signal. A delay and divide circuit receives an incoming CMI encoded signal and produces a signal that has transitions corresponding to the bit boundaries of the CMI signal. This signal is then passed through a clock recovery loop (i.e., a phase-locked loop) to synchronize a clock signal with a CMI signal. The clock recovery loop further includes a delay circuit that adjusts the timing of the feedback signal such that it matches the delay of the CMI signal that occurs as the CMI signal passes through the delay and divide circuit. Accordingly, the circuit adjusts the timing of the recovered clock signal until it matches the clocking of the incoming CMI signal.
Claims24
An apparatus comprising:
- a first signal-conditioning circuit having an input to receive a Coded Mark Inversion (CMI) signal and having an output, said first signal-conditioning circuit to produce a first delayed signal having a first delay;
- a timing recovery loop circuit having a first input connected to the output of the first signal-conditioning and a second input and an output, said timing recovery loop to produce a loop reference signal comprising a recovered clock signal having a frequency in accord with a clocking of the CMI signal;
- and
- a second signal-conditioning circuit to cause a delay to the loop reference signal to generate a second delay signal that has a second delay that matches the first delay of the first delayed signal, comprising a divide-by-one circuit including:
- an XOR gate having a first input to receive the recovered clock signal, a second input, and an output;
- and
- a D-type flip-flop having a CLK input connected to the output of the XOR gate, a D input and Q and Qbar outputs, said Qbar output connected to said D input, said Q output connected to the second input of the XOR gate, said divide-by-one circuit having an output at said Q output connected to the second input of the timing recovery loop circuit.
4 more elements
An apparatus comprising:
- a first signal-conditioning circuit having an input to receive a Coded Mark Inversion (CMI) signal and having an output, said first signal-conditioning circuit to produce a first delayed signal having a first delay;
- a timing recovery loop circuit having a first input connected to the output of the first signal-conditioning and a second input and an output, said timing recovery loon to produce a loop reference signal comprising a recovered clock signal having a frequency in accord with a clocking of the CMI signal;
- and
- a second signal-conditioning circuit to cause a delay to the loon reference signal to generate a second delay signal that has a second delay that matches the first delay of the first delayed signal, comprising a divide-by-one circuit including:
- an XOR gate having a first input to receive the recovered clock signal and a second input to receive a clock quadrature signal and an output, said clock quadrature signal being delayed relative to said recovered clock signal by one-fourth of the period of the recovered clock signal;
- and
- a D-type flip flop having a CLK input connected to the output of the XOR gate, a D input, and Q and Qbar outputs, said D input to receive an inverted recovered clock signal, said divide-by-one circuit output corresponding to said Q output connected to the second input of the timing recovery loop circuit.
4 more elements
An apparatus comprising:
- first signal-conditioning circuit having an input to receive a Coded Mark Inversion (CMI) signal and having an output, said first signal-conditioning circuit to produce a first delayed signal having a first delay;
- a timing recovery loop circuit having a first input connected to the output of the first signal-conditioning and a second input and an output, said timing recovery loop to produce a loop reference signal comprising a recovered clock signal having a frequency in accord with a clocking of the CMI signal;
- and
- a second signal-conditioning circuit to cause a delay to the loop reference signal to generate a second delay signal that has a second delay that matches the first delay of the first delayed signal, comprising a divide-by-one circuit including:
- a quad-input XNOR gate including a first input to receive the recovered clock signal and a second input to receive a clock quadrature signal and a pair of complimented outputs, said clock quadrature signal being delayed relative to said recovered clock signal by one-fourth of the period of the recovered clock signal;
- and
- a negative edge triggered D-type flip flop having a CLK input to receive the complimented outputs of the quad-input XNOR gate, and D inputs and Q and Qbar outputs, said D input to receive an inverted recovered clock signal, said divide-by-one circuit output corresponding to said Q output.
4 more elements
An apparatus comprising:
- a first signal-conditioning circuit having an input for receiving a Coded Mark Inversion (CMI) signal and having an output, said first signal-conditioning circuit to produce a first delayed signal having a first delay;
- a phase-locked loop circuit including:
- a phase detection circuit having a first input connected to the output of the first conditioning circuit and a second input connected to the output of the second conditioning circuit and at least one output, said phase detection circuit to produce a phase adjustment signal to align a timing of the first delayed signal and the second delayed signal
- a loop filter comprising an integration circuit having an input connected to said at least one output of the phase detection circuit and an output;
- and
- a controlled oscillator, having an input connected to the output of the integration circuit, and to produce a loop reference signal comprising a recovered clock signal having a frequency in accord with a clocking of the CMI signal;
- and
- a second signal-conditioning circuit to cause a delay to the loop reference signal to generate a second delay signal that has a second delay that matches the first delay of the first delayed signal, said second-siqnal-conditioning circuit comprising a divide-by-one circuit including:
- an XOR gate having a first Input to receive the recovered clock signal, a second input, and an output;
- and
- a D-tvpe flip-flop having a CLK Input connected to the output of the XOR gate, a D input and Q and Qbar outputs, said Qbar output connected to said D input, said Q output connected to the second input of the XOR gate, said divide-by-one circuit having an output at said Q output connected to the second input of the timing recovery loot circuit.
8 more elements
A method for recovering a clock signal from a Coded Marked Inversion (CMI) signal, comprising:
- causing a delay to the CMI signal to produce a first delayed signal having a first delay relative to a timing of the CMI signal;
- inputting the first delayed signal and a second delayed signal through a timing recovery loop to produce a recovered clock signal;
- and
- causing a delay to the recovered clock signal to produce the second delayed signal, said second delayed signal having a second delay relative to a timing of the recovered clock signal and being produced by:
- receiving the recovered clock signal at a first input of an XOR gate;
- clocking a D-type flip flop with an output of the XOR gate at a CLK input of the D-type flip-flop, said D-type flip-flop having a D input and Q and Qbar outputs, said Qbar output connected to said D input, said Q output connected to a second input of the XOR gate;
- and
- producing the second delayed signal at the Q output of the D flip-flop,
- wherein the first and second delayed signals have matched delays relative to their respective input signals.
6 more elements
Dependencies are inferred from the claim text.