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US 6,748,014 B1Granted
Correlator/FIR filter unit for dual-mode transceiver
AssigneeIndustrial Technology Research Institute
InventorsFu-Yen Kuo, Chung-Wei Ku
Life of this patent
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Abstract
A Time Division Multiple Access (TDMA) and Code Division Multiple Access (CDMA) transceiver in which correlator banks consisting of an array of dual-code correlators (two tri-code correlators) are used to form correlator filters, such as chip matched filters or multi-code RAKE receivers, or FIR filters for CDMA/TDMA related applications.
Claims10
A chip matched filter for a dual-mode transceiver comprising:
- a controller for calculating I and Q symbols;
- a plurality of upper dual-code correlator banks connected to said controller for receiving an input from an I-branch and correlating I and Q codes;
- and
- a plurality of lower dual-code correlator banks connected to said controller for receiving an input from a Q-branch and correlating I and Q codes, wherein each of said upper and lower dual-code correlator banks includes a plurality of dual-code correlators, wherein each of said dual-code correlators further comprises:
- a data delay unit for delaying said input corresponding to said I-branch or said Q-branch;
- a pair of accumulators for correlating said delayed input from said data delay unit and a pair of code serial inputs;
- and
- a plurality of registers for storing data from said accumulators.
5 more elements
A chip matched filter for a dual-mode transceiver comprising:
- a controller for calculating I and Q symbols;
- a plurality of upper dual-code correlator banks connected to said controller for receiving an input from an I-branch and correlating I and Q codes;
- and
- a plurality of lower dual-code correlator banks connected to said controller for receiving an input from a Q-branch and correlating I and Q codes, wherein each of said upper and lower dual-code correlator banks includes a plurality of dual-code correlators, wherein each of said dual-code correlators includes a pair of tri-code correlators having a common input.
1 more element
A RAKE receiver for a dual-mode transceiver comprising:
- a controller for calculating I and Q symbols;
- a plurality of upper dual-code correlator banks connected to said controller for receiving input from an I-branch and correlating I and Q channels with four PN codes;
- and
- a plurality of lower dual-code correlator banks connected to said controller for receiving input from a Q-branch and correlating I and Q channels with four PN codes, wherein each of said upper and lower dual-code correlator banks includes a plurality of dual-code correlators,
- wherein each of said upper and lower dual-code correlator banks further comprises:
- a linear array of said dual-code correlators;
- and
- an address decoder for addressing said array of dual-code correlators,
- and wherein each of said dual-code correlators further comprises:
- a data delay unit for delaying said input corresponding to said I-branch or said Q-branch;
- a pair of accumulators for correlating said delayed input from said data delay unit and a pair of code serial inputs;
- and
- a plurality of registers for storing data from said accumulators.
10 more elements
A RAKE receiver for a dual-mode transceiver comprising:
- a controller for calculating I and Q symbols;
- a plurality of upper dual-code correlator banks connected to said controller for receiving input from an I-branch and correlating I and Q channels with four PN codes;
- and
- a plurality of lower dual-code correlator banks connected to said controller for receiving input from a Q-branch and correlating I and Q channels with four PN codes, wherein each of said upper and lower dual-code correlator banks includes a plurality of dual-code correlators,
- wherein each of said dual-code correlators includes a pair of tri-code correlators having a common input.
2 more elements
A finite-impulse response (FIR) filter for a dual-mode transceiver comprising:
- a controller for calculating I and Q symbols;
- a pair of upper dual-code correlator banks connected to said controller for receiving data from an I-branch and processing FIR coefficients in a canonical signed digit (CSD) format;
- and
- a pair of lower dual-code correlator banks connected to said controller for receiving data from a Q-branch and processing said FIR coefficients in said CSD format, wherein each of said upper and lower dual-code correlator banks includes an array of dual-code correlators, and
- wherein each of said dual-code correlators further comprises:
- a data delay unit for delaying said input;
- a pair of accumulators for correlating said delayed input from said data delay unit and said FIR coefficients;
- and
- a plurality of registers for storing data from said accumulators.
6 more elements
A finite-impulse response (FIR) filter for a dual-mode transceiver comprising:
- a controller for calculating I and Q symbols;
- a pair of upper dual-code correlator banks connected to said controller for receiving data from an I-branch and processing FIR coefficients in a canonical signed digit (CSD) format;
- and
- a pair of lower dual-code correlator banks connected to said controller for receiving data from a Q-branch and processing said FIR coefficients in said CSD format, wherein each of said upper and lower dual-code correlator banks includes an array of dual-code correlators, and
- wherein each of said dual-code correlators includes a pair of tri-code correlators having a common input.
2 more elements
A method for processing a signal through a finite-impulse response (FIR) filter comprising the steps of:
- calculating I and Q symbols using a controller;
- and
- processing FIR coefficients in a canonical signed digit (CSD) format using pairs of left and right dual-code correlator banks connected to said controller, and
- wherein two least significant bits (LSBS) of said FIR coefficients in CSD format are sent to said pair of left dual-code correlators, and two most significant bits (MSBs) of said FIR coefficients in CSD format are sent to said pair of right dual-code correlators.
1 more element
A tri-code correlator, comprising:
- a correlator, receiving an input and a code serial input for accumulation;
- and
- a control unit, receiving an enabling signal, for activating or deactivating said correlator for accumulation, wherein said correlator comprises:
- an XOR gate for processing said input and said the code serial input;
- and
- a two's compliment adder for accumulating said code serial input, an output of said XOR gate and an output of an register, and sending an output of a two's compliment adder to an input of said register which couple to said control unit for accumulation.
3 more elements
A tri-code correlator, comprising:
- a correlator, receiving an input and a code serial input for accumulation;
- and
- a control unit, receiving an enabling signal, for activating or deactivating said correlator for accumulation, wherein said control unit further comprises:
- an AND gate, receiving said enabling signal, for activating or deactivating said correlator for accumulation.
1 more element
Dependencies are inferred from the claim text.