Clock synchronized non-volatile memory device

A nonvolatile memory apparatus comprising:

• a control circuit;
• a plurality of terminals including a clock terminal, a command terminal and an other terminal;
• a plurality of nonvolatile memory cells;
• a first volatile memory;
• and
• a second volatile memory,
• wherein said clock terminal is capable of receiving a first clock signal,
• wherein said command terminal is capable of receiving commands which comprise a read command and a program command,
• wherein said control circuit reads out operation steps from a program memory for controlling an operation of said received command by executing said operation steps,
• wherein in an operation in response to said read command received from said command terminal, said control circuit controls, based on operation steps corresponding to said read command, reading of data from ones of said nonvolatile memory cells, stores a read data to said second volatile memory, transfers said read data from said second volatile memory to said first volatile memory, and outputting said read data from said first volatile memory via said other terminal except saod command terminal in response to said first clock signal, and
• wherein an operation in response to said program command received from said command terminal, said control circuit controls, based on operation steps corresponding to said program command, receiving of data via said other terminal except said command terminal in response to said first clock signal, stores a received data to said first volatile memory, transferring said received data from said first volatile memory to said second volatile memory, and writing said received data from said second volatile memory to ones of said nonvolatile memory cells.