Implied precharge and posted activate command to reduce command bandwidth
AssigneeIntel Corporation
InventorRobert J. Riesenman
Life of this patent
Estimating the term…
Abstract
A combination precharge/activate command is utilized in order to make more efficient use of a command bus between a memory controller and a system memory. Upon receiving a precharge/activate command from the memory controller, the system memory makes a determination as to how to interpret the command depending on a page status. For an open page, the precharge/activate command is treated as a precharge command and then the system memory performs an activate with proper command timing using address and bank given during precharge/activate command. For a closed page, the precharge/activate command is treated as an activate command.
Claims16
A memory controller, comprising:
- a clock signal output;
- a plurality of command signal outputs, the plurality of command signal outputs to deliver a precharge/activate inferred command to a first bank of a memory device at a first clock edge, the precharge/activate inferred command to be interpreted by the memory device as an activate command;
- a plurality of address line outputs, the plurality of address line outputs to deliver a first row address to the memory device at the first clock edge;
- and
- a plurality of data line outputs.
A memory module, comprising:
- a clock signal input;
- a plurality of command signal inputs, the plurality of command signal inputs to receive a precharge/activate inferred command for a first bank of memory at a first clock edge, the precharge/activate inferred command to be interpreted as an activate command;
- a plurality of address line inputs, the plurality of address line inputs to receive a first row address at the first clock edge;
- and
- a plurality of data line inputs.
A system, comprising:
- a processor;
- a system memory device;
- and
- a memory controller coupled to the processor and also coupled to the system memory device, the memory controller including
- a clock signal output,
- a plurality of command signal outputs, the plurality of command signal outputs to deliver a precharge/activate inferred command to a first bank of the system memory device at a first clock edge, the precharge/activate inferred command to be interpreted by the memory device as an activate command,
- a plurality of address line outputs, the plurality of address line outputs to deliver a first row address to the system memory device at the first clock edge, and
- a plurality of data line outputs.
A method, comprising:
- delivering a precharge/activate inferred command to a first bank of a memory device at a first clock edge, the precharge/activate inferred command to be interpreted by the memory device as an activate command;
- and
- delivering a first row address to the memory device at the first clock edge.
Dependencies are inferred from the claim text.