Synchronous memory with open page

A flash memory device comprising:

• an array of non-volatile memory cells arranged in rows and columns;
• latch circuitry coupled to store a row of data read from the memory array;
• and
• control circuitry coupled to place the memory device in a low power mode, wherein the memory device maintains power to the latch circuitry during the low power mode, the control circuitry allows the stored data in the latch circuitry to be read by an external device following a termination of the low power mode, wherein the data read from the latch circuitry following termination of the low power consumption mode has a shorter clock latency with respect to the external device than reading data from the array.

A memory system comprising:

• a processor;
• and
• a flash memory device coupled to the processor, the flash memory device comprises,
• an array of non-volatile memory cells arranged in rows and columns,
• latch circuitry coupled to store a row of data read from the memory array, and
• control circuitry to receive an externally provided command from the processor to place the memory device in a low power mode, wherein the memory device maintains power to the latch circuitry during the low power mode such that the row of data can be output when the memory device exits the low power mode.

A flash memory device comprising:

• an array of non-volatile memory cells arranged in rows and columns;
• latch circuitry coupled to store a row of data read from the memory array;
• and
• control circuitry to place the memory device in a low power mode by decoupling power to the array, wherein the memory device maintains power to the latch circuitry during the low power mode, the control circuitry allows the stored data in the latch circuitry to be read by an external device following a termination of the low power mode, wherein accessing the stored data in the latch circuitry is performed in less clock cycles than reading data stored in the array.

A method of operating a memory device comprising:

• reading a row of data from a memory array of the memory device;
• storing the read row data in a volatile latch circuit;
• in response to an externally provided command, activating a first power supply to the array to place the array in a low power mode;
• and
• maintaining a second power supply to the latch circuit such that an integrity of the read row data is maintained during the low power mode.

A method of operating a flash memory device comprising:

• accessing a page of data of a memory array;
• latching the accessed page;
• in response to an externally provided command, powering down the flash memory device to a low power state, such that array access circuitry of the flash memory device is non-functional;
• powering up the flash memory device such that the array access circuitry is functional;
• reading the latched page while the array access circuitry of the flash memory device is non-functional.

A method of operating a flash memory device comprising:

• accessing a page of data of a memory array;
• latching the accessed page;
• powering down the flash memory device to a low power state, such that a voltage pump provided to generate an elevated access voltage is turned off;
• powering up the flash memory device such that the voltage pump is turned on, wherein the voltage pump requires X seconds to reach a stable pumped output voltage;
• and
• reading the latched page during the X seconds and prior to the voltage pump reaching a stable pumped output voltage.