Semiconductor memory device and method of selecting word line thereof

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cell array blocks, the memory cell array block including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines;
• a plurality of sub word line drivers each including alternatively an odd-numbered sub word line driver and an even-numbered sub word line driver between each of the plurality of the partial blocks, the odd-numbered sub word line driver for outputting odd-numbered first signals to the odd-numbered sub word lines in response to a first row decoding signal transferred to the global word line, the even-numbered sub word line driver for even-numbered first control signals to the even-numbered sub word lines in response to the first row decoding signal;
• a plurality of sense amplifying means arranged on upper and lower sides of the plurality of the memory cell array blocks and between the neighboring partial blocks and performing a sensing operation in response to first and second sense amplifier control signals;
• a plurality of drivers alternatively arranged on crossing points of each of the plurality of the sub word line drivers and each of the plurality of the sense amplifying means, each of the plurality of the drivers including an odd-numbered driver and an even-numbered driver, the odd-numbered driver for outputting odd-numbered second row decoding signals as the odd-numbered first signal in response to a control signal to control the corresponding partial block and a control signal to control the neighboring partial block, the even-numbered driver for outputting even-numbered row decoding signals as the even-numbered first signal;
• a plurality of sense amplifier control means arranged on upper and lower sides of the crossing points alternately with the plurality of the drivers, and generating first and second sense amplifier control signals for respective sense amplifying means arranged on left and right sides thereof in response to a corresponding sense amplifier enable signal generated in response to a block selecting signal generated to select the corresponding memory cell array block and a control signal to control the corresponding partial block;
• an odd-numbered partial block control signal generating means for generating a control signal when a first selecting signal to select the odd-numbered corresponding partial block or a second selecting signal to select the partial block previous to the corresponding partial block is input in case that the odd-numbered sub word lines of the odd-numbered partial block are selected, and when the first selecting signal or a third selecting signal to select the partial block next to the corresponding partial block is input in case that the even-numbered sub word lines are selected;
• and
• an even-numbered partial block control signal generating means for generating a control signal when a fourth selecting signal to select a corresponding even-numbered partial block or a fifth selecting signal to select the partial block next to the corresponding even-numbered partial block is input in case that the odd-numbered sub word lines of the even-numbered partial block are selected, and when the fourth selecting signal or a sixth selecting signal to select the partial block previous to the corresponding even-numbered partial block in case that the even-numbered sub word lines is selected.

A semiconductor memory device which includes

• a memory cell array including
• a) memory cell array blocks;
• b) partial blocks of each of the memory cell array blocks;
• c) global word lines arranged over the memory cell array blocks;
• d) first sub word line drivers arranged on a left side of the odd-numbered partial blocks and connected to the odd-numbered sub word lines of the previous partial block and the odd-numbered partial blocks;
• e) second sub word line drivers arranged on a left side of the even-numbered partial blocks and connected to the even-numbered sub word lines of the previous partial block and the even-numbered partial blocks;
• f) first drivers arranged on either of upper and lower sides of the first sub word line drivers and receiving a first sub word line decoding signal;
• g) second drivers arranged on either of upper and lower sides of the second sub word line drivers and receiving a second sub word line decoding signal;
• h) bit line sense amplifiers arranged on upper and lower sides of each of the partial blocks;
• and
• i) sensing enable control signal generating means arranged in turn on a region of left and right sides of the bit line sense amplifier except the first and second drivers;
• a first row decoder for generating a signal applied to the drivers and applied to the sub word line drivers;
• a second row decoder for generating a global word line selecting signal to select the global word line;
• and
• a column decoder, the device comprising,
• a control means receiving a row address to select the sub word line and selecting signals of a corresponding partial block, the previous partial block and a next partial block which are output signals of the column decoder, and generating selecting control signals to select the partial block to be activated among the plurality of the partial blocks,
• wherein, among the pselecting control signals, a corresponding partial block selecting control signal and a neighboring partial block selecting control signal are input into the first and second drivers to activate the sub word lines together with the first and second sub word line decoding signals.

A method of selecting word lines of a semiconductor memory device including a plurality of memory cell array blocks, each of the memory cell array blocks including a plurality of partial blocks, a plurality of global word lines, and a predetermined number of sub word lines corresponding to each of the plurality of the global word lines, the method comprising:

• generating a global word line selecting signal for selecting the global word line by decoding a plural-bit first row address;
• generating a sub word line selecting signal for selecting the sub word line by decoding a plurali-bit second row address;
• selecting the partial block having the sub word lines to be activated by combining parts of the plural-bit second row address and a column address;
• and
• activating only the sub word lines of the partial block by combining the global word line, the partial block activation signal and the sub word line selecting signal.

A semiconductor memory device, comprising:

• a plurality of memory cell array blocks each including a plurality of partial blocks in one of either a first or a second partial block group,
• a plurality of global word lines;
• a plurality of sub word lines in one of either a first or second sub word line group, corresponding to each of the plurality of the global word lines, wherein:
• in partial blocks of the first partial block group, sub word lines of the first sub word line group are connected to sub word lines of the first sub word line group of a previous block, and sub word lines of the second sub word line group are connected to sub word lines of the second sub word line group of a next partial block;
• and
• in partial blocks in the second partial block group, sub word lines of the first sub word line group are connected to sub word lines of the first sub word line group of the next partial block, and sub word lines of the second sub word line group are connect to sub word lines of the second sub word line group of a previous partial block;
• and
• a control means for selecting sub word lines of a corresponding partial block and sub word lines of a neighboring partial block connected to the sub word lines of the corresponding partial block when the corresponding partial block is selected in response to externally applied row and column address.

A semiconductor memory device, comprising:

• a plurality of memory cell array blocks each including a plurality of partial blocks of either a first or second group, a plurality of global word lines, and sub word lines of either a first or second group corresponding to each of the plurality of the global word lines, the sub word lines of the first group of each of partial blocks of a first group among the plurality of the partial blocks, respectively, connected to the sub word lines of the first group of each of the previous neighboring partial blocks, the sub word lines of a second group of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the sub word lines of the second group of each of the next neighboring partial blocks, the sub word lines of the first group of each of partial blocks of the second group among the plurality of the partial blocks, respectively, connected to the sub word lines of the first group of each of the next neighboring partial blocks, the sub word lines of the second group of each of the partial blocks of the second group among the plurality of the partial blocks, respectively, connected to the sub word lines of the first group of each of the previous neighboring partial blocks;
• and
• a plurality of sub word line drivers each including alternatively a first group sub word line driver and a second group sub word line driver between each of the plurality of the partial blocks, the sub word line driver of the first group for outputting first signals of the first group to the sub word lines of the first group in response to a first row decoding signal transferred to the global word line, the sub word line driver of the second group for first control signals of the second group to the sub word lines of the second group in response to the first row decoding signal.