Configurable decoder for addressing a memory

A method of reading from a memory comprising:

• receiving an address portion comprising a first number of bits;
• blocking a second number of bits of the address portion, the second number less than the first number;
• passing a third number of bits of the address portion, wherein the third number summed with the second number is equal to the first number;
• reading a fourth number of data bits from a fourth number of memory cells;
• and
• decoding the third number of bits to multiplex a fifth number of data bits to a fifth number of outputs.

An integrated circuit comprising:

• an address conforming logic block configured to receive a first number of address bits, block a second number of address bits, and pass a third number of address bits;
• an address decoder coupled to the address conforming logic block configured to decode the third number of address bits and provide a fourth number of column select signals;
• and
• a memory array having memory cells arranged in rows and columns, configured to receive the fourth number of column select signals.

An integrated circuit comprising:

• an address conforming logic block configured to receive a first number of address bits, block a second number of address bits, and pass a third number of address bits;
• an address decoder coupled to the address conforming logic block configured to decode the third number of address bits and provide a fourth number of column select signals;
• a memory array having memory cells arranged in rows and a fifth number of columns;
• and
• a fifth number of sense amplifiers coupled to the memory array, configured to provide a fifth number of read data bits.

An integrated circuit comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• address configuration means for receiving a plurality of address bits comprising a first portion of address bits and a second portion of address bits, blocking the first portion of address bits, and providing the second portion of address bits;
• address decoder means for receiving the second portion of address bits and providing a plurality of select lines, wherein the plurality of select lines selects a plurality of columns of memory cells in the memory array;
• and
• data multiplexer means for receiving a plurality of data bits and the plurality of select lines, and multiplexing the plurality of data bits to the plurality of columns of memory cells in the memory array.

An integrated circuit comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• sense amplifier means for reading data from the columns of memory cells in the memory array and providing a plurality of read data bits;
• address configuration means for receiving a plurality of address bits comprising a first portion of address bits and a second portion of address bits, blocking the first portion of address bits, and providing the second portion of address bits;
• address decoder means for receiving the second portion of address bits and providing a plurality of select lines;
• and
• data multiplexer means for receiving the plurality of read data bits and the plurality of select lines, and multiplexing a first portion of the plurality of read data bits to a plurality of output data lines.