Memory circuit arrangement for programming a memory cell
AssigneeAdvanced Micro Devices, Inc.
InventorsSheunghee Park, Ming Sang Kwan
Life of this patent
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Abstract
A memory circuit for programming a target cell is disclosed. According to one embodiment, the memory circuit comprises the target cell having a drain terminal connected to a bit line. A drain voltage is coupled to the bit line and supplies a voltage greater than a ground voltage, while a gate voltage is coupled to a gate terminal of the target cell and supplies a voltage greater the ground voltage. A source voltage is coupled to a source terminal of the target cell and supplies a voltage less than the ground voltage, and a substrate voltage is coupled to a substrate of the target cell and supplies a voltage less than the ground voltage.
Claims20
A memory Circuit for programming a target cell, said memory circuit comprising:
- said target cell having a drain terminal connected to a bit line;
- a drain voltage coupled to said bit line, said drain voltage being greater than a ground voltage;
- a gate voltage coupled to a gale terminal of said target cell, said gate voltage being greater than said ground voltage;
- a source voltage coupled to a source terminal of said target cell, said source voltage being less than said ground voltage;
- and
- a substrate voltage coupled to a substrate of said target cell, said substrate voltage being less than said ground voltage, wherein said drain voltage, gate voltage, source voltage, and substrate voltage cause electrons to be generated and attracted to a floating gate of said target cell.
A memory circuit for programming a target cell, said memory circuit comprising:
- target memory means for storing at least one bit, said target memory means comprising said target cell having a drain terminal connected to a bit line;
- first voltage means for supplying a drain voltage, said drain voltage coupled to said bit line, said drain voltage being greater than a ground voltage
- second voltage means for supplying a gale voltage, said gate voltage coupled to a gate terminal of said target cell, said gate voltage being greater than said ground voltage;
- third voltage means for supplying a source voltage, said source voltage coupled to a source terminal of said target cell, said source voltage being less than said ground voltage;
- and
- fourth voltage means for supplying a substrate voltage, said substrate voltage coupled to a substrate of said target cell, said substrate voltage being less than said ground voltage, wherein said drain voltage, gate voltage, source voltage, and substrate voltage cause electrons to be generated and attracted to a floating gate of said target cell.
A memory circuit for programming a target cell, wherein said target cell has a drain terminal connected to a bit line, a drain voltage is coupled to said bit line and said drain voltage is greater than a ground voltage;
- and wherein a gate voltage is coupled to a gate terminal of said target cell, said gate voltage is greater than said ground voltage and a source voltage is coupled to a source terminal of said target cell;
- and further wherein a substrate voltage is coupled to a substrate of said target cell, said memory circuit being characterized in that:
- said source voltage is less than said ground voltage and said substrate voltage is less than said ground voltage, wherein said drain voltage, gate voltage, source voltage, and substrate voltage cause electrons to be generated and attracted to a floating gate of said target cell.
Dependencies are inferred from the claim text.