Column decode circuit for high density/high performance memories

A Flash memory Y-Mux circuit, comprising:

• a memory array with a plurality of sense amplifiers;
• an address interface coupled to an address decoder;
• and
• a plurality of decode lines coupled to the address decoder and routed on a conductor process layer of the memory array that is separate from an array ground of the memory array, wherein a single pass transistor is coupled to each sense amplifier and each decode line is coupled to at least one pass transistor.

A Flash memory device, comprising:

• a memory array containing a plurality of floating gate memory cells;
• an address interface coupled to a row address decoder and a column address decoder;
• and
• a plurality of column decode lines coupled to the column address decoder and routed on a conductor process layer of the memory array that is separate from an array ground of the memory array, wherein the column decode circuit is adapted to fully decode a column address and wherein each column decode line is coupled to a single pass transistor.

A non-volatile memory array, comprising:

• a plurality of sense amplifiers;
• an address decoder;
• and
• a plurality of decode lines coupled to the address decoder and routed into the memory array on a conductor process layer of the memory array that is separate from an array around of the memory array, wherein a single pass transistor is coupled to each sense amplifier and wherein each decode line is coupled to at least one pass transistor.

A Flash memory device, comprising:

• a memory array with a plurality of memory banks, wherein each memory bank has a plurality of read sense amplifiers and a plurality of write sense amplifiers;
• a data input bus coupled to a data buffer, wherein each write sense amplifier is coupled to the data input bus with a single pass transistor;
• a data output bus coupled to the data buffer, wherein each read sense amplifier is coupled to the data output bus with a single pass transistor;
• an address interface coupled to a row address decoder and a column address decoder, wherein the column address decoder is a single logic level and is adapted to fully decode the column address;
• and
• a plurality of column select lines coupled to the column address decoder, wherein each column select line is coupled to at least one pass transistor, and wherein each column select line is formed in a metal layer of the memory array that is separate from an array ground of the memory array.

A system, comprising:

• a processor;
• and
• a Flash memory device coupled to the processor, wherein the Flash memory device comprises:
• a memory array containing a plurality of floating gate memory cells;
• an address interface coupled to a row address decoder and a column address decoder;
• and
• a plurality of column decode lines coupled to the column address decoder and muted into the memory array on a conductor process layer of the memory array that is separate from an array ground of the memory array, wherein the column decode circuit is adapted to fully decode a column address and wherein each column decode line is coupled to a single pass transistor.

A method of operating a Flash memory device, comprising:

• receiving a memory access containing a memory address at a memory device;
• decoding the memory address with an address decoder;
• and
• accessing a memory array of the Flash memory device by activating at least one decode select line of a plurality of decode select lines routed into the memory array on a conductor process layer of the memory array that is separate from an array ground of the memory array, wherein each of the at least one decode select lines selectively couples at least one sense amplifier to a data bus with a pass transistor.

A method of making a Flash memory device, comprising:

• forming a memory array with a plurality of sense amplifiers that each couple to a data bus with a single pass transistor;
• forming an address interface;
• forming an address decode circuit coupled to the address interface;
• and
• forming a plurality of decode select lines on a conductor process layer of the memory array that is separate from an array ground of the memory array, each decode select line coupled to the address decoder and at least one of the pass transistors.

A method of operating a Flash memory device, comprising:

• receiving a memory access containing a column address at a memory device;
• fully decoding the column address with a column address decoder;
• and
• accessing a memory array of the Flash memory device by activating at least one decode select line of a plurality of decode select lines, wherein each of the at least one decode select lines is routed through a metal process layer over the memory array and selectively couples at least one sense amplifier to a data bus with a Y-MUX, wherein the metal process layer is separate from an array ground of the memory array.

A Flash memory device, comprising:

• a memory array containing a plurality of floating gate memory cells;
• a plurality of bit lines, wherein each bit line is coupled to a sense amplifier and to a plurality of outputs of the plurality of floating gate memory cells;
• an address interface coupled to a row address decoder and a column address decoder;
• a plurality of column decode lines coupled to the column address decoder, wherein the column address decoder is adapted to fully decode a column address and wherein each column decode line is routed through a metal process layer of the memory array that is separate from an array around of the memory array;
• and
• a Y-MUX, wherein each Y-MUX is coupled to one or more column decode lines and selectively couples a plurality of the sense amplifiers to a bus in response to an output of column address decoder coupled via the column decode lines.