Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system

A data deletion method for a nonvolatile semiconductor memory, the nonvolatile semiconductor memory comprising:

• a memory cell comprising second semiconductor regions for a source and a drain, respectively, formed in a first semiconductor region in a semiconductor substrate;
• a charge accumulation layer formed on a region between said second semiconductor regions for the source and the drain through a gate insulating film;
• and a control electrode provided on said charge accumulation layer through an insulating film;
• and
• a third semiconductor region formed between said first semiconductor region and the semiconductor substrate, wherein
• the data deletion method comprising the steps of:
• applying a first voltage to said control electrode, applying a second voltage to said first semiconductor region, and pulling out electrons accumulated in said charge accumulation layer into said first semiconductor region based on a potential difference between said first voltage and said second voltage in a first period;
• determining a threshold voltage of said memory cell in a second period following said first period;
• and
• applying the first voltage to said control electrode, applying the second voltage to said first semiconductor region and thereby pulling out the electrons accumulated in said charge accumulation layer into said first semiconductor region in a third period following said second period if the threshold voltage of said memory cell is higher than a predetermined threshold voltage, and wherein
• a third voltage is applied to said third semiconductor region during said first to third periods.

A nonvolatile semiconductor memory comprising:

• (a) a memory cell comprising second semiconductor regions for a source and a drain, respectively, formed in a first semiconductor region in a semiconductor substrate;
• a charge accumulation layer formed on a region between said second semiconductor regions for the source and the drain through a gate insulating film;
• and a control electrode provided on said charge accumulation layer through an insulating film;
• (b) a third semiconductor region (NiSO) formed between said first semiconductor region and the semiconductor substrate;
• (c) first means for applying a voltage to said control electrode;
• (d) second means for applying a voltage to said first semiconductor region;
• and
• (e) third means for prohibiting a voltage from being applied to said third semiconductor region, and
• (f) means for determining a threshold voltage of said memory cell,
• wherein the conductive type of said first semiconductor region is a p type and that of said third semiconductor region is an n type,
• a first voltage is applied to said control electrode and a second voltage is applied to said first semiconductor region in a first period, thereby allowing electrons accumulated in said charge accumulation layer to be pulled out into said first semiconductor region,
• the threshold voltage of said memory cell is determined in a second period following said first period,
• if it is determined that the threshold voltage of said memory cell is higher than a predetermined threshold voltage, the first voltage is applied to said control electrode and the second voltage is applied to said first semiconductor region in a third period following said second period, thereby allowing the electrons accumulated in said charge accumulation layer to be pulled out into said first semiconductor region,
• a second voltage is applied to said first semiconductor region in said first period and thereby said third semiconductor region is charged through said first semiconductor region up to said second voltage, and
• said third semiconductor region is maintained in a floating state during said first to third periods.

A data deletion method for a nonvolatile semiconductor memory, the nonvolatile semiconductor memory comprising:

• a memory cell comprising second semiconductor regions for a source and a drain, respectively, formed in a first semiconductor region in a semiconductor substrate;
• a charge accumulation layer formed on a region between said second semiconductor regions for the source and the drain through a gate insulating film;
• and a control electrode provided on said charge accumulation layer through an insulating film;
• and
• a third semiconductor region formed between said first semiconductor region and the semiconductor substrate, wherein
• the data deletion method comprises the steps of:
• applying a first voltage to said control electrode, applying a second voltage to said first semiconductor region, and pulling out electrons accumulated in said charge accumulation layer into said first semiconductor region based on a potential difference between said first voltage and said second voltage in a first period;
• determining a threshold voltage of said memory cell in a second period following said first period;
• and
• applying the first voltage to said control electrode, applying the second voltage to said first semiconductor region and thereby pulling out the electrons accumulated in said charge accumulation layer, into said first semiconductor region in a third period following said second period if the threshold voltage of said memory cell is higher than a predetermined threshold voltage, and wherein
• the conductive type of said first semiconductor region is a p type and that of said third semiconductor region is an n type,
• a second voltage is applied to said first semiconductor region in said first period and thereby said third semiconductor region is charged through said first semiconductor region up to said second voltage, and
• said third semiconductor region is maintained in a floating state during said first to third periods.

A nonvolatile semiconductor memory comprising:

• (a) a plurality of memory cell groups each having a plurality of memory cells formed on a main surface of a first semiconductor region in a semiconductor substrate, each memory cell comprising second semiconductor regions for a source and a drain, respectively, formed in said first semiconductor region;
• a charge accumulation layer formed on a region between the second semiconductor regions for the source and the drain through a gate insulating film;
• and a control electrode provided on said charge accumulation layer through an insulating film;
• (b) a third semiconductor region formed between said first semiconductor region and the semiconductor substrate;
• (c) first voltage application means for applying a voltage to said control electrode;
• and
• (d) second voltage application means for applying a voltage to said first semiconductor region and said third semiconductor region, respectively, wherein
• said third semiconductor region is separated at intervals units of a predetermined number of the memory cells in the plurality of memory cell groups.