Sense amplifier for multilevel non-volatile integrated memory devices

A sense amplifier to read a multi-state memory cell having a field effect transistor (FET) with a source, a drain and a bit-line, the sense amplifier comprising:

• a device coupled to the drain of the FET of the memory cell, the device adapted to increase the resolution of the sense amplifier during a read mode and to isolate the sense amplifier from a high voltage applied to the memory cell during a write mode;
• and
• a pre-charge circuit coupled to the cascode device, the pre-charge circuit configured to pre-charge the bit-line of the memory cell through a cascode device during a pre-charge mode to reduce time required to read the multi-state memory cell,
• wherein the pre-charge circuit comprises a unity gain buffer having an input to which a predetermined reference voltage is applied, and an output coupled to provide a bias current(IBIAS) to the cascode device to pre-charge the bit-line by charging a node of the cascode device to the predetermined reference voltage.

In a memory having at least one multi-state memory cell capable of storing data therein and a sense amplifier capable of reading data stored in the memory cell, the sense amplifier having a cascode device coupled to the memory cell and a pre-charge circuit for pre-charging a bit-line of the memory cell through the cascode device, a method of operating the memory to read data stored in the multi-state memory cell, the method comprising the steps of:

• coupling the pre-charge circuit to the cascode device;
• pre-charging the bit-line of the memory cell through the cascode device to a predetermined reference voltage;
• de-coupling the pre-charge circuit from the cascode device;
• developing a voltage signal representing data stored in the memory cell;
• reconfiguring the pre-charge circuit as a regeneration circuit;
• and
• amplifying the voltage signal using the regeneration circuit such that the amplified voltage signal increasingly deviates from the predetermined reference voltage with increasing time.

A multi-state memory comprising:

• at least one multi-state memory cell capable of storing data therein;
• a sense amplifier capable or reading data stored in the memory cell, the sense amplifier including:
• a cascode device coupled to the memory cell;
• a pre-charged circuit for pre-charging a bit-line of the at least one multi-state memory cell through the cascode device;
• a developing circuit for developing a voltage signal representing data stored in the memory cell using a reference current;
• and
• an amplifying circuit for amplifying the voltage signal such that the amplified voltage signal increasingly deviates from the predetermined reference voltage with increasing time.

A multi-state memory comprising:

• at least one multi-state memory cell capable of storing data therein;
• a sense amplifier capable or reading data stored in the memory cell, the sense amplifier including:
• a cascode device coupled to the memory cell;
• a pre-charged circuit for pre-charging a bit-line of the at least one multi-state memory cell through the cascode device;
• a developing circuit for developing a voltage signal representing data stored in the memory cell using a reference current;
• and
• an amplifying circuit for amplifying the voltage signal,
• wherein the pre-charging circuit comprises a unity gain buffer having an input to which a predetermined reference voltage is applied, and an output coupled to provide a bias current (IBIAS) to the cascode device to pre-charge the bit-line by charging the node of the cascode device to the predetermined reference voltage.