Ternary content addressable memory device

A content addressable memory (CAM) having an array of cells arranged in rows and columns, each cell comprising:

• a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement;
• a compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node;
• a match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal;
• a discharge circuit coupled to ground;
• a precharge circuit coupled to a preset voltage;
• the discharge circuit or the precharge circuit coupled to the match input line of the same row or the match output line of the same row,
• wherein when all cells of the same row output a match, all the match input and output lines of the same row are either precharged or discharged.

A method of operating a content addressable memory (CAM) having an array of cells arranged in rows and columns, comprising the steps of:

• storing in a main memory cell a data bit and its complement;
• comparing the data bit and its complement with signals at corresponding compare lines and outputting a compared signal;
• selectively connecting a match input line to a match output line based on an indication of a match from the compared signal to form a match line;
• and
• setting the match line at a first voltage level when all of memory cells of the same row are matched.