Clamping circuit for stacked NMOS ESD protection

A circuit for protecting integrated semiconductor active devices from damage due to ESD voltages applied to an input or output signal pad said circuit comprising:

• at least one switching circuit string composed of a first and second used NMOS device and a used PMOS device wherein the gate of said first used NMOS device is connected to a first voltage source and the drain element of said first used NMOS device is connected to said input/output signal pad and to the drain element of said used PMOS device, and the source of said first used NMOS device is connected to the drain element of said second used NMOS device and the gates of said second used NMOS and said used PMOS are connected to an internal circuit and the source of said used second NMOS is connected to a second voltage source, and the source of said used PMOS is connected to said first voltage source;
• a discharging means for discharging positive charges accumulated on said gate of said second used NMOS wherein said discharging means are connected to said internal circuit and said discharging circuit string to prevent said second used NMOS from turning on from said ESD voltage occurrence;
• and
• at least one circuit string consisting of a first and second unused dummy NMOS device and an unused dummy PMOS device, wherein the gate of said first unused dummy NMOS device is connected to a first voltage source and the drain element of said first unused dummy NMOS device is connected to said input/output signal pad and to the drain element of said unused dummy PMOS device, and the source of said first unused dummy NMOS device is connected to the drain element of said second unused dummy NMOS device;
• and the gate and source of said second unused dummy NMOS are connected to said second voltage source and the gate and drain of said unused dummy PMOS are connected to said first voltage source.

A method of forming a clamped circuit for stacked NMOS ESD protection comprising:

• connecting source region of a used PMOS device and source and gate of an unused PMOS device to a first voltage source;
• connecting the drains of said used and unused PMOS devices to said stacked NMOS input/output pad;
• connecting the drain of said used PMOS device to a drain of a first used NMOS device, and the drain of said unused PMOS device to a drain of a first unused NMOS device;
• connecting the gate of said used PMOS device to a logic signal line;
• connecting the gates of said first used and said first unused NMOS devices to said first voltage source;
• connecting the source of said first used NMOS device to the drain of a second used NMOS device and the source of said first unused NMOS device to the drain of a second unused NMOS device;
• connecting the source of said second used NMOS and the source and gate of said second unused NMOS device to a second voltage source;
• and
• connecting the gate of said second used NMOS device to said logic signal line and to a discharging means for discharging positive charges accumulated on said gate of said second used NMOS.