Image data processing system

An image data processing system comprising:

• an image memory for storing a color code, an output port of the image memory being electrically connected to a display;
• a processor for storing the color code in the image memory;
• an address controller electrically connected to both the processor and the image memory for storing the color code in a plurality of addresses of the image memory according to the address information of an image area received from the processor, and the plurality of addresses of the image memory storing the color code corresponding to at least two pixels of the image area;
• a display controller electrically connected to both the display and the address controller for transmitting the color code stored in the image memory to the display via the address controller, and controlling the operations of the display so that the display shows a first image according to the color code;
• and
• a second multiplexer comprising:
• two input ports electrically connected to the output port of the image memory and an external image input port, respectively, the external image input port being used to input external image data so that the display is able to show a second image;
• and
• an output port electrically connected to the input port of the display, the display controller controlling the exhibitions of the first image and the second image via the second multiplexer so that both the first image and the second image overlap when shown on the display.

An image data processing system comprising:

• 2N color code registers for storing a plurality of color codes;
• a first multiplexer electrically connected to every output port of the 2N color code registers, the first multiplexer comprising a control port for inputting an N-bit image code, the first multiplexer choosing one of the outputs of the 2N color code registers as output according to the N-bit image code;
• a processor for storing 2N color codes in the 2N color code registers, and periodically transmitting a plurality of N-bit image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the 2N color code registers as output according to one of to N-bit image codes;
• an image memory electrically connected to an output port of the first multiplexer for storing a plurality of color code received from the first multiplexer;
• an address controller electrically connected to both the processor and the image memory for storing the plurality of color codes received from the first multiplexer into a predetermined address of the image memory according to a command from the processor;
• a mode controller for storing a mode code from the processor;
• and a third multiplexer comprising two input ports, an output port, and a control port, the two input ports of the third multiplexer electrically connected to the output port of the first multiplexer and an output port of a predetermined color code register from the plurality of color code registers, respectively, and the output port and control port of the third multiplexer being electrically connected to the input port of the image memory and the output port of the mode controller, respectively the processor being able to store a color code in the predetermined color code register, the third multiplexer choosing the output of the predetermined color code register according to the mode code so that the color code stored in the predetermined color code register is stored into a predetermined address of the image memory.