Error correction architecture to increase speed and relax current drive requirements of SAR ADC

A method of operating an SAR ADC to convert an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) sampling the analog input voltage and redistributing a charge representative of the sampled analog input voltage among a coupling capacitance and a plurality of binarily weighted capacitors of a CDAC array to produce a voltage on a charge summing conductor;
• (b) performing a successive approximation bit testing/conversion operation at a first speed for each bit except a least significant bit of a first group of M bits of the output word, beginning with the MSB, to determine with at least a first level of accuracy whether each bit except the least significant bit of the first group is a “1” or a “0”, where M and N are integers and M is less than N;
• (c) performing an error correction operation at a second speed, the error correction operation including performing a bit testing/conversion operation on the least significant bit of the first group at a second speed which is lower than the first speed to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then performing an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and incrementing or decrementing the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to the second level of accuracy, and correspondingly incrementing or decrementing the voltage on the charge summing conductor.

A method of increasing the speed of operation of an SAR ADC to convert an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) sampling the analog input voltage and redistributing a charge representative of the sampled analog input voltage among a coupling capacitance and a plurality of binarily weighted capacitors of a CDAC array to produce a voltage on a charge summing conductor;
• (b) performing a successive approximation bit testing/conversion operation at a first speed for each bit except a least significant bit of a first group of M bits of the output word, beginning with the MSB, to determine with at least a first level of accuracy whether each bit except the least significant bit of the first group is a “1” or a “0”, where M and N are integers and M is less than N;
• and
• (c) performing an error correction operation at a second speed, the error correction operation including performing a bit testing/conversion operation on the least significant bit of the first group at a second speed which is lower than the first speed to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then performing an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and incrementing or decrementing the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to the second level of accuracy, and correspondingly incrementing or decrementing the voltage on the charge summing conductor.

A method of operating an SAR ADC to convert an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) sampling the analog input voltage and redistributing a charge representative of the sampled analog input voltage among a coupling capacitance and a plurality of binarily weighted capacitors of a CDAC array to produce a voltage on a charge summing conductor;
• (b) performing a successive approximation bit testing/conversion operation at a first speed for each of a first number of bits constituting a first group of M bits of the output word except a least significant bit of the first group, beginning with the most significant bit of the output word, to determine values of the bits except the least significant bit of the first group with at least a first level of accuracy, wherein M and N are integers and M is less than N;
• (c) performing an error correction operation at a second speed which is lower than the first speed, the error correction operation including performing a bit testing/conversion operation on the least significant bit of the first group to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then performing an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and incrementing or decrementing the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to the second level of accuracy, and correspondingly incrementing or decrementing the voltage on the charge summing conductor;
• and
• (d) performing the successive approximation bit testing/conversion operation on at least some of the remaining N-M bits at a speed which is lower than the first speed at an accuracy that is at least as accurate as the second level of accuracy.

A method of operating an SAR ADC to convert an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) sampling the analog input voltage and redistributing a charge representative of the sampled analog input voltage among a coupling capacitance and a plurality of binarily weighted capacitors of a CDAC array to produce a voltage on a charge summing conductor;
• (b) performing a successive approximation bit testing/conversion operation at a first speed for each of a first number of bits constituting a first group of bits of the output word except a least significant bit of the first group, beginning with the most significant bit of the output word, to determine with at least a first level of accuracy whether each bit except the least significant bit of the first group is a “1” or a “0”;
• (c) performing an error correction operation at a second speed which is lower than the first speed, the error correction operation including performing a bit testing/conversion operation on a least significant bit of the first group to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then performing an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and incrementing or decrementing the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to at least the second level of accuracy, and correspondingly incrementing or decrementing the voltage on the charge summing conductor;
• and
• (d) for each of a second number of bits constituting a second group of bits of the output word, beginning with a most significant bit in the second group, performing a successive approximation bit testing/conversion operation at a second speed to determine values of the bits of the second group with at the second level of accuracy.

A method of operating an SAR ADC to convert an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) sampling the analog input voltage and redistributing a charge representative of the sampled analog input voltage among a coupling capacitance and a plurality of binarily weighted capacitors of a CDAC array to produce a voltage on a charge summing conductor;
• (b) performing a successive approximation bit testing/conversion operation at a first speed and at a first level of accuracy on each bit except a least significant bit of a first group of bits of the output word, beginning with a most significant bit of the first group, to determine with a first level of accuracy whether each bit except the least significant bit of the first group is a “1” or a “0”;
• (c) performing an error correction operation at a second speed which is lower than the first speed, the error correction operation including performing a bit testing/conversion operation on the least significant bit of the first group to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then performing an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and incrementing or decrementing the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to the second level of accuracy, and correspondingly incrementing or decrementing the voltage on the charge summing conductor;
• (d) for each of a second number of bits constituting a second group of bits of the output word except a least significant bit of the second group, beginning with a most significant bit of the second group, performing the successive approximation bit testing/conversion operation at a second speed and at the second level of accuracy on each bit except a least significant bit of the second group, beginning with a most significant bit of the second group, to determine with the second level of accuracy whether each bit except the least significant bit of the second group is a “1” or a “0”;
• (e) performing the bit testing/conversion operation on the least significant bit of the second group at a third speed which is lower than the second speed to determine whether a value of the least significant bit of the second group is a “1” or a “0” and then performing an error correction operation to determine a value of the bits of the second group to at least a third level of accuracy which is more accurate than the second level of accuracy, and incrementing or decrementing the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the second group to the third level of accuracy, and correspondingly incrementing or decrementing the voltage on the charge summing conductor.

An SAR ADC for converting an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) a sampling capacitance for coupling the analog input voltage;
• (b) a CDAC capacitor array for receiving and redistributing a charge representative of the sampled analog input voltage among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor;
• (c) a comparator having a first input coupled to the charge summing conductor and a second input coupled to receive a reference voltage;
• (d) SAR control circuitry coupled to an output of the comparator to perform a successive approximation bit testing/conversion operation at a first speed and at a first level of accuracy on each bit except a least significant bit of a first group of bits of the output word, beginning with a most significant bit of the first group, to determine whether each bit except the least significant bit of the first group is a “1” or a “0”;
• (e) the SAR control circuitry being operative to perform an error correction operation at a second speed which is lower than the first speed, the error correction operation including performing a bit testing/conversion operation on the least significant bit of the first group to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then performing an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and to increment or decrement the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to the second level of accuracy and correspondingly increment or decrement the voltage on the charge summing conductor.

An SAR ADC for converting an analog input voltage to an output word including N bits including a most significant bit, comprising:

• (a) a coupling capacitance for sampling the analog input voltage;
• (b) a CDAC capacitor array for receiving and redistributing a charge representative of the sampled analog input voltage among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor;
• (c) a comparator having a first input coupled to the charge summing conductor and a second input coupled to receive a reference voltage;
• (d) SAR control circuitry coupled to an output of the comparator to perform a successive approximation bit testing/conversion operation at a first speed and at a first level of accuracy on each bit except a least significant bit of a first group of bits of the output word, beginning with a most significant bit of the first group, to determine whether each bit except the least significant bit of the first group is a “1” or a “0”;
• (e) the SAR control circuitry being operative to perform an error correction operation at a second speed which is lower than the first speed, the error correction operation including performing a bit testing/conversion operation on the least significant bit of the first group at a second speed which is lower than the first speed to determine whether a value of the least significant bit of the first group is a “1” or a “0” and then perform an incrementing/decrementing operation to determine a value of the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy, and to increment or decrement the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the first group to the second level of accuracy and correspondingly increment or decrement the voltage on the charge summing conductor;
• (f) the SAR control circuitry being operative to perform the successive approximation bit testing/conversion operation at the second speed and at the second level of accuracy on each bit except a least significant bit of a second group of bits of the output word, beginning with a most significant bit of the second group, to determine whether each bit except the least significant bit of the second group is a “1” or a “0”;
• (g) the SAR control circuitry being operative to perform the error correction operation at a third speed which is lower than the second speed, the error correction operation including performing the bit testing/conversion operation on the least significant bit of the second group to determine whether a value of the least significant bit of the second group is a “1” or a “0” and then perform an incrementing/decrementing operation to determine a value of the bits of the second group to at least a third level of accuracy which is more accurate than the second level of accuracy, and to increment or decrement the least significant bit of the first group as necessary to elevate the level of accuracy of the bits of the second group to the third level of accuracy and correspondingly increment or decrement the voltage on the charge summing conductor.

An SAR ADC for converting an analog input voltage to an output word including N bits including an MSB, comprising:

• (a) means for sampling the analog input voltage and redistributing a charge representative of the sampled analog input voltage among a coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor;
• (b) means for performing a successive approximation bit testing/conversion operation at a first speed for each of a first number of bits constituting a first group of bits of the output word, beginning with a most significant bit of the first group to determine values of the bits of the first group with a first level of accuracy;
• (c) means for performing an error correction operation at a second speed which is lower than the first speed, the error correction operation including performing a first error correction operation by performing a bit testing/conversion operation on a least significant bit of the first group to determine a value of the bits of the first group with a second level of accuracy which is more accurate than the first level of accuracy;
• and
• (d) means for incrementing or decrementing the bits of the first group as necessary to elevate the level of accuracy of bits of the first group to the second level of accuracy and correspondingly incrementing or decrementing the voltage on the charge summing conductor.