Analog memory cell in a low power oscillator
AssigneeZeevo, Inc.
InventorStephen Allott
Life of this patent
Estimating the term…
Abstract
An analog memory cell that may be incorporated into a low power oscillator is provided. The analog memory cell stores an analog voltage as a digital signal and converts the digital signal back to an analog voltage to allow continued generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the analog memory cell in the low power oscillator is fully implementable in a CMOS process.
Claims20
A low power oscillator, comprising:
- a voltage controlled oscillator having an input and an output, the output configured to provide an output signal of substantially constant frequency;
- and
- an analog memory cell in electrical communication with the input of the voltage controlled oscillator, the analog memory cell configured to provide a voltage to the input of the voltage controlled oscillator, the analog memory cell having digital circuitry that includes a latch configured to provide a constant digital output signal when activated, and the analog memory cell including digital-to-analog conversion circuitry for receiving the constant digital output signal from the latch and outputting the voltage provided to the voltage controlled oscillator, wherein the voltage remains substantially constant when the latch is activated.
An analog memory cell, comprising:
- digital-to-analog conversion circuitry configured to receive a first digital control signal and provide an output voltage;
- comparator circuitry in electrical communication with the digital-to-analog conversion circuitry, the comparator circuitry configured to receive the output voltage from the digital-to-analog conversion circuitry, the comparator circuitry further configured to receive an input voltage, the comparator circuitry configured to compare the output voltage and the input voltage to generate a second digital control signal;
- and
- digital circuitry in electrical communication with both the comparator circuitry and the digital-to-analog conversion circuitry, the digital circuitry comprising a successive approximation logic block, an integration logic block, and a digital signal latch, the digital circuitry configured to receive the second digital control signal from the comparator circuitry, the digital circuitry further configured to process the second digital control signal through either the successive approximation logic block or the integration logic block to generate the first digital control signal, the digital signal latch capable of latching the first digital control signal.
A method for providing a substantially constant voltage to operate a low power oscillator, comprising:
- operating a phase lock loop comprising an analog memory cell;
- operating the analog memory cell in a coarse mode to adjust a voltage generated by the analog memory cell;
- acquiring a loop lock by operating the analog memory cell in the coarse mode;
- operating the analog memory cell in a fine mode to adjust the voltage generated by the analog memory cell, wherein the voltage adjustments provided by the fine mode are of substantially small size relative to the voltage adjustments provided by the coarse mode;
- and
- latching a digital signal in the analog memory cell, wherein the digital signal provides an input to digital-to-analog conversion circuitry, wherein the input to digital-to-analog conversion circuitry dictates the voltage generated by the analog memory cell.
Dependencies are inferred from the claim text.