Phase-locked loop with automatic frequency tuning
AssigneeAdvanced Micro Devices, Inc.
InventorsRolf Jaehne, Wolfram Kluge, Thorsten Riedel
Life of this patent
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Abstract
A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.
Claims17
A PLL frequency synthesizer, comprising:
- a voltage controlled oscillator in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator;
- a phase/frequency detector for generating an error signal based on a frequency input signal and a PLL feedback signal;
- and
- an operating mode determining unit for determining one of the operating modes of the voltage controlled oscillator based on the error signal,
- wherein said operating mode determining unit includes a window comparator configured to compare the error signal with predefined upper and lower error voltage limits for switching to adjacent operating modes when the error signal exceeds or falls below the upper or lower error voltage limits and includes a delay counter for delaying the switching between adjacent operating modes, and wherein the operating frequency ranges of adjacent operating modes overlap by predefined portion of the respective operating frequency range.
A method for controlling the operation of a voltage controlled oscillator in a PLL frequency synthesizer, said voltage controlled oscillator being operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator, comprising the steps of:
- generating an error signal based on a frequency input signal and a PLL feedback signal;
- determining one of the operating modes of the voltage controlled oscillator based on the error signal, wherein said determining step compares the error signal with predefined upper and lower error voltage limits for switching to adjacent operating modes when the error signal exceeds or falls below the upper or lower error voltage limits;
- and
- delaying a switching signal by a predetermined time period, said switching signal for switching to an adjacent operating range, wherein the operating frequency ranges of adjacent operating modes overlap by predefined portion of the respective operating frequency range.
Dependencies are inferred from the claim text.