Semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a plurality of memory mats including plural memory cells each having a selection terminal connected to a word line and being arranged like an array;
• word drivers which selectively drives the word lines, regularly provided between said memory mats arranged like an array;
• a plurality of sets of MOS logic circuits which supply a word-line driving voltage to said word drivers, regularly provide between said memory mats arranged like an array;
• first sub-power supply lines extending in a first direction, each of which is connected to at least a corresponding one of said plurality of sets of MOS logic circuits so that a plurality of said MOS logic circuits are arranged along each of said first sub-power supply lines in said first direction,
• second sub-power supply lines, extending in a second direction perpendicular to said first direction, each connected to two or more of said first sub-power supply lines at intersection portions thereof;
• a main power supply line extending in said second direction so that said logic circuits are arranged along said first sub-power lines to extend perpendicular to said main power supply line;
• and
• a plurality of switching MOS transistors which respectively connect said first sub-power supply lines to said main power supply line,
• wherein said switching MOS transistors are kept off in a standby state of said MOS logic circuits and kept on in an operable state of the MOS logic circuits.

A semiconductor integrated circuit comprising:

• a plurality of memory mats including plural memory cells each having a selection terminal connected to a word line and being arranged like an array;
• word drivers which selectively drives the word lines, regularly provided between said memory mats arranged like an array;
• a plurality of sets of MOS logic circuits which supply a word-line driving voltage to said word drivers, regularly provide between said memory mats arranged like an array;
• first sub-power supply lines, extending in a first direction, each of which is connected to at least a corresponding one of said plurality of sets of MOS logic circuits so that a plurality of said MOS logic circuits are arranged along each of said first sub-power supply lines in said first direction,
• second sub-power supply lines, extending in a second direction perpendicular to said first direction, connected to said first sub-power supply lines at intersection portions thereof;
• a main power supply line extending in said second direction so that said logic circuits are arranged along said first sub-power lines to extend perpendicular to said main power supply line;
• and
• a plurality of switching MOS transistors which respectively connect said first sub-power supply lines to said main power supply line,
• wherein said switching MOS transistors are kept off in a standby state of said MOS logic circuits and kept on in an operable state of the MOS logic circuits,
• wherein a selection signal is supplied to a group of said word drivers from a common main word line, said sets of MOS logic circuits supply a word line driving level of said first sub-power supply lines to said word drivers in accordance with a decoding signal for selecting one of said word drivers, and
• wherein said first sub-power supply lines are formed with the same wiring layer as the main word line.