US 6,747,507 B1 · Bias generator with improved stability for self biased phase locked loop

Abstract

A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP4; a second transistor MP3 coupled in parallel with the first transistor MP4; an amplifier A1 having a first input coupled to the first and second transistors MP4 and MP3, and to a gate of the second transistor MP3, and a second input coupled to a control voltage node VCTRL; a third transistor MN4 coupled in series with the first transistor MP4; a fourth transistor MN2 coupled in series with the third transistor MN4 and having a gate coupled to an output of the amplifier A1; a fifth transistor MP1; a sixth transistor MP2 coupled in parallel with the fifth transistor MP1; a seventh transistor MN3 coupled in series with the fifth transistor MP1; and an eighth transistor MN1 coupled in series with the seventh transistor MN3 and having a gate coupled to a gate of the fourth transistor MN2. In order to maintain the bias generator stability for different biasing conditions, the feed-forward path is removed by diode connecting the second transistor MP3 instead of connecting the gate of the second transistor MP3 to the control voltage node VCTRL.

Claims11

Dependent claims

A bias generator circuit comprising:

a first transistor;
a second transistor having a first end coupled to a first end of the first transistor, a second end coupled to a second end of the first transistor, and a gate coupled to a gate of the first transistor;
an amplifier having a first input coupled to the second end of the first transistor and to the gate of the second transistor, and a second input coupled to a control voltage node;
a third transistor having a first end coupled to the second end of the first transistor;
a fourth transistor having a first end coupled to a second end of the third transistor and having a gate coupled to an output of the amplifier;
a fifth transistor;
a sixth transistor having a first end coupled to a first end of the fifth transistor, a second end coupled to a second end of the fifth transistor, and a gate coupled to a gate of the fifth transistor;
a seventh transistor having a first end coupled to the second end of the fifth transistor;
and
an eighth transistor with a first end coupled to a second end of the seventh transistor and having a gate coupled to a gate of the fourth transistor;
and
wherein the first, second, fifth, and sixth transistors are PMOS transistors;
and the third, fourth, seventh, and eighth transistors are NMOS transistors.

10 more elements

Dependencies are inferred from the claim text.

Bias generator with improved stability for self biased phase locked loop

Life of this patent

Bias generator with improved stability for self biased phase locked loop

Life of this patent

Abstract

Claims11