US 6,747,500 B2 · Compact delay circuit for CMOS integrated circuits used in low voltage low power devices

Abstract

A low voltage, low power versatile and compact delay circuit for CMOS integrated circuits. The biasing circuit and comparator of the delay circuit are implemented with a relatively few simple transistor stages. This approach makes the circuit compact and allows for operation at very low supply voltages (e.g., 1.5 volts). The time delay of the delay circuit is made to depend only on passive resistive and capacitive components. The time delay is thus insensitive to fluctuations in the supply voltage, as well as fluctuations in temperature. This configuration is particularly advantageous in circuits where several timing elements need to track with one another, as they can all be formed with resistors and capacitors of the same construction. The design also makes the circuit insensitive to process parameters, as well as later environmental effects due to operating temperature, circuit aging, and the like. A common signal is used to control both a trip point voltage of a comparator and a voltage change rate of a clock ramp signal in the delay circuit, such that variations in voltage supplied to the clock during normal operation does not substantially affect the clock period.

Claims49

Dependent claims

A low voltage low power delay circuit for determining a delay time interval comprising:

a bias circuit portion for generating first and second bias signals;
a ramp generator portion comprising at least one capacitor and a first transistor coupled to a first terminal of the at least one capacitor, the ramp generator generating a voltage ramp signal wherein a voltage change rate of the voltage ramp signal is controlled by a current level in the first transistor, the first transistor having a gate coupled to the bias circuit portion such that the current level in the first transistor is controlled by the first bias signal, the ramp generator further comprising a switch coupled to the at least one capacitor, the switch being operable by a reset signal so as to reset the voltage on the at least one capacitor;
a comparator portion comprising a second transistor having a gate coupled to receive the voltage ramp signal, wherein a switching threshold voltage at the gate of the second transistor is controlled by a current level in a third transistor coupled to the second transistor, the third transistor having a gate coupled to the bias circuit portion such that the current level in the third transistor is controlled by the second bias signal;
and
wherein a relationship between the voltage change rate of the ramp signal and the switching threshold voltage is at least partially governed by the first and second bias signals such that the delay time interval determined by the delay circuit tends to be stabilized against variations in a supply voltage supplied to the delay circuit during normal operation.

2 more elements

A low voltage low power delay circuit for determining a delay time interval comprising:

a bias circuit portion for generating first and second bias signals;
a ramp generator portion comprising a capacitor and a first transistor coupled to a first terminal of the capacitor, the ramp generator generating a voltage ramp signal wherein a voltage change rate of the voltage ramp signal is controlled by a current level in the first transistor, the first transistor having a gate coupled to the bias circuit portion such that the current level in the first transistor is controlled by the first bias signal, the ramp generator further comprising a reset switch coupled to the capacitor, the reset switch being operable by a reset signal so as to reset the voltage on the capacitor;
and
a comparator portion comprising a second transistor having a gate coupled to receive the voltage ramp signal, wherein a switching threshold voltage at the gate of the second transistor is controlled by a current level in a third transistor coupled to the second transistor, the third transistor having a gate coupled to the bias circuit portion such that the current level in the third transistor is controlled by the second bias signal;
and
wherein a relation ship between the voltage change rate of the ramp signal and the switching threshold voltage is at least partially governed by the first and second bias signals such that the delay time interval determined by the delay circuit tends to be stabilized against temperature-induced variations in the operating characteristics of at least the first, second and third transistors during normal operation.

3 more elements

Dependencies are inferred from the claim text.

Compact delay circuit for CMOS integrated circuits used in low voltage low power devices

Life of this patent

Compact delay circuit for CMOS integrated circuits used in low voltage low power devices

Life of this patent

Abstract

Claims49