DLL-(delay-locked-loop) circuit
AssigneeInfineon Technologies AG
InventorChristian Reindl
Life of this patent
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Abstract
The present invention provides a Delay Locked Loop circuit having: a delay device for generating at least one delayed clock signal from an input clock signal; a phase detector for comparing the delayed clock signal with the input clock signal; a first control device for generating a first control signal for influencing a delay time of the delay device; a device for generating a signal Q, whose frequency is proportional to the reciprocal of the delay time of the delay device; a device for evaluating the signal Q and generating an output signal; and a second control device for modifying the first control signal in accordance with the output signal. The present invention likewise provides a method for generating a control signal of a Delay Locked Loop circuit.
Claims23
A Delay Locked Loop circuit having:
- a delay device for generating at least one delayed clock signal from an input clock signal;
- a phase detector for comparing the delayed clock signal with the input clock signal;
- a first control device connected to said phase detector for generating a first control signal for influencing a delay time of the delay device;
- a device for generating a signal Q, whose frequency is proportional to the reciprocal of the delay time of the delay device;
- a device connected to said device for generating a signal Q for receiving the signal Q and generating an output signal;
- and
- a second control device connected to said device for receiving the signal Q for adjusting the frequency of the first control signal in accordance with the output signal.
Method for generating at least one delayed clock signal synchronously with an input clock, which is delayed exactly by one period with respect to the input clock signal, having the following steps:
- generating at least one delayed clock signal from an input clock signal;
- comparing the delayed clock signal with the input clock signal;
- generating a first control signal for influencing a delay time of a delay device;
- generating a signal Q, whose frequency is proportional to the reciprocal of the delay time of the delay device;
- evaluating the signal Q and generating an output signal;
- and
- modifying the first control signal in accordance with the output signal.
Dependencies are inferred from the claim text.