Power-on reset circuit

A power-on reset circuit comprising:

• an input circuit which is initialized by the assertion of a power-on reset signal entered from outside when power supply is turned on or is initialized when a detection signal of a first logical value is entered and, when said power-on reset signal is negated and said detection signal of a second logical value is entered, supplies a first signal of a third logical value in synchronization with an external clock signal,
• a reset extending circuit which is initialized by the assertion of said power-on reset signal and, after said power-on reset signal is negated, supplies a second signal which takes on a fourth logical value when an external clock signal is first entered and a fifth logical value after the lapse of a prescribed length of time determined by counting said external clock signals after said first signal of said third logical value is entered,
• a detecting circuit which is initialized by the assertion of said power-on reset signal and, after said power-on reset signal is negated, caused to generate said detection signal of said second logical value by the input of said second signal of said fourth logical value from said reset extending circuit in synchronism with said external clock signal and supply it to said input circuit, and
• a gate circuit which supplies a reset signal of a prescribed logical value when the first signal of said third logical value is supplied from said input circuit and said second signal of said fifth logical value is supplied from said reset extending circuit.