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US 6,747,492 B2Granted
Power-on reset circuit with current shut-off and semiconductor device including the same
AssigneeKoninklijke Philips Electronics N.V.
InventorsAlok Govil, Vickram Vathulya
Life of this patent
Estimating the term…
Abstract
A power-on reset circuit input stage includes a current source charging a capacitor from a first power supply voltage to produce a reset signal, and a current shutoff means for shutting off the current source when the reset signal reaches a desired threshold voltage (i.e., when the capacitor is charged up). Beneficially, the current shutoff means comprises a transistor connected between the current source and a second power supply voltage. Advantageously, the transistor is controlled by a feedback voltage that may be the output signal, or a voltage derived from the output signal by a capacitive divider, for example.
Claims31
A power-on reset circuit input stage, comprising:
- first and second transistors each having first and second terminals and a control terminal, the first terminal of each of the first and second transistors being connected to a first power supply voltage, and the control terminals of the first and second transistors being connected to each other and to the second terminal of the first transistor;
- a first capacitor connected between the second terminal of the second transistor and a second power supply voltage;
- a third transistor having first and second terminals and a control terminal, the second terminal of the third transistor being connected to the second power supply voltage;
- a resistor connected between the second terminal of the first transistor and the first terminal of the third transistor;
- and
- a second capacitor that is one of (1) directly connected in series between the second terminal of the second transistor and the first capacitor and (2) connected between the control terminal of the third transistor and the second power supply terminal,
- wherein the control terminal of the third transistor is adapted to respond to a voltage across the first capacitor to selectively turn on and turn off the third transistor and a current charging the first capacitor.
4 more elements
A power-on reset circuit input stage, comprising:
- first and second transistors each having first and second terminals and a control terminal, the first terminal of each of the first and second transistors being connected to a first cower supply voltage, and the control terminals of the first and second transistors being connected to each other and to the second terminal of the first transistor;
- a first capacitor connected between the second terminal of the second transistor and a second power supply voltage;
- a third transistor having first and second terminals and a control terminal, the second terminal of the third transistor being connected to the second cower supply voltage;
- and
- a resistor connected between the second terminal of the first transistor and the first terminal of the third transistor,
- wherein the control terminal of the third transistor is adapted to respond to a voltage across the first capacitor to selectively turn on and turn off the third transistor and a current charging the first capacitor, and wherein the control terminal of the third transistor is connected to the second terminal of the second transistor and the first capacitor.
3 more elements
A power-on reset circuit input stage, comprising:
- first and second transistors each having first and second terminals and a control terminal, the first terminal of each of the first and second transistors being connected to a first power supply voltage, and the control terminals of the first and second transistors being connected to each other and to the second terminal of the first transistor;
- a first capacitor connected between the second terminal of the second transistor and a second power supply voltage;
- a third transistor having first and second terminals and a control terminal, the second terminal of the third transistor being connected to the second power supply voltage;
- and
- a resistor connected between the second terminal of the first transistor and the first terminal of the third transistor,
- wherein the control terminal of the third transistor is adapted to respond to a voltage across the first capacitor to selectively turn on and turn off the third transistor and a current charging the first capacitor, and wherein the first, second end third transistors are PMOS transistors.
3 more elements
A power-on reset circuit input stage, comprising:
- a first capacitor;
- a current source supplying current to the first capacitor and producing therefrom an output voltage, the current source comprising,
- a current mirror having a first terminal connected to a first power supply voltage,
- current shutoff means for shutting off the current supplied to the first capacitor when a voltage across the first capacitor reaches a threshold voltage level, and
- a resistor connected between the current mirror and the current shutoff means;
- and
- a second capacitor that is one of (1) connected in series with the first capacitor between the current mirror and a second power supply voltage, (2) connected between a control terminal of the current shutoff means and the second power supply voltage, and (3) connected between the output voltage and the control terminal of the current shutoff means.
4 more elements
A power-on reset circuit, comprising:
- a current mirror connected to a first power supply voltage;
- a first capacitor receiving current from the current mirror;
- current shutoff means connected between the current mirror and a second power supply voltage, the current shutoff means being adapted to shut off the current received by the first capacitor when a voltage across the first capacitor reaches a threshold voltage level;
- and
- a second capacitor that is one of (1) connected in series with the first capacitor between the current mirror and the second power supply voltage, (2) connected between the control terminal of the first transistor and the second power supply voltage, and (3) connected between the first capacitor and the control terminal of the transistor.
2 more elements
A semiconductor integrated circuit, comprising:
- a digital circuit having a reset input;
- a power-on reset circuit, comprising
- an input stage, including:
- a current mirror connected to a first power supply voltage,
- a first capacitor receiving current from the current mirror and providing an output signal, and
- current shutoff means connected between the current mirror and a second power supply voltage, the current shutoff means being adapted to shut off the current received by the first capacitor when a voltage across the first capacitor reaches a threshold voltage level, and
- an output stage, including means for converting the output signal into a reset signal applied to the reset input;
- and
- a second capacitor that is one of (1) connected in series with the first capacitor between the current mirror and the second power supply voltage, (2) connected between a control terminal of the current shutoff means and the second power supply voltage, and (3) connected between the first capacitor and the control terminal of the transistor.
6 more elements
Dependencies are inferred from the claim text.