Spike free circuit for reducing EMI effect
AssigneeWinbond Electronics Corp.
InventorHideharu Koike
Life of this patent
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Abstract
The present invention discloses a spike free circuit, which comprises a first flip-flop stage, a time shift means, a group of logic gates and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a clock signal. The time shift means is electrically connected to the first flip-flop stage and triggered by a second edge opposite to the first edge of the clock signal. The time shift means shifts input signals, which change logic level within the first to the second edges of the clock signal one half cycle for preventing spike occurring. The group of logic gates is connected to the time shift means. The second flip-flop stage is electrically connected to the group of logic gates and triggered by the first edge of the clock signal.
Claims11
A spike free circuit, comprising:
- a first flip-flop stage triggered by a first edge of a clock signal;
- and
- a time shift means electrically connected to the first flip-flop stage and triggered by a second edge opposite to the first edge of the clock signal, the time shift means shifting input signals which changes logic level within the first to the second edges of the clock signal one half cycle for preventing spike occurring;
- a group of logic gates connected to the time shift means;
- and
- a second flip-flop stage electrically connected to the group of logic gates and triggered by the first edge of the clock signal.
Dependencies are inferred from the claim text.