Sampling pulse generation
AssigneeIntel Corporation
InventorsJames E. Jaussi, Bryan K. Casper, Joseph T. Kennedy, Stephen R. Mooney
Life of this patent
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Abstract
According to some embodiments, a circuit provides a first set of one or more flip-flops to receive a low-swing differential clock, and a second set of one or more flip-flops to receive the low-swing differential clock. One of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.
Claims25
A circuit comprising:
- a first set of one or more flip-flops to receive a low-swing differential clock;
- and
- a second set of one or more flip-flops to receive the low-swing differential clock,
- wherein one of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.
A method comprising:
- receiving a low-swing differential clock signal;
- generating a first CMOS-level sampling pulse for each cycle of the low-swing differential clock with one of one or more flip-flops of a first set of flip-flops;
- and
- generating a second CMOS-level sampling pulse for each cycle of the low-swing differential clock with one of one or more flip-flops of a second set of flip-flops.
A flip-flop to receive a low-swing differential clock signal and to generate a CMOS-level sampling pulse based on the low-swing differential clock signal.
A system comprising:
- a delay lock loop to receive a differential clock signal and to generate a plurality of phases of the differential clock signal;
- an interpolator to receive the plurality of phases, to receive a code, and to generate a low-swing differential clock signal based on the received plurality of phases and on the received code;
- and
- a pulse generator to receive the low-swing differential clock signal, to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock with one of one or more flip-flops of a first set of flip-flops, and to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock with one of one or more flip-flops of a second set of flip-flops.
A system comprising:
- a chipset;
- and
- a die comprising a microprocessor in communication with the chipset, wherein the microprocessor includes a receiver comprising:
- a pulse generator to receive the low-swing differential clock signal, to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock with one of one or more flip-flops of a first set of flip-flops, and to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock with one of one or more flip-flops of a second set of flip-flops.
Dependencies are inferred from the claim text.