US 6,747,483 B2 · Differential memory interface system

Abstract

A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.

Claims21

Dependent claims

A memory interface system comprising:

a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit, wherein the differential control interface is configured to drive a first and a second differential control output signal, and wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common;
and
a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each single-ended memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, wherein the buffer unit is coupled with the first power supply, and the buffer unit is configured to transfer data between the differential control interface and the single-ended memory interface.

A memory interface system for transferring data, the system comprising a control driver configured to drive a first and a second control output signal, the control driver comprising:

a first current source coupled with a first power supply, the first current source configured to provide a control output current;
a first switching unit coupled with the first current source, the first switching unit configured to switch based on a first control input signal;
a first resistive bias unit coupled with the first switching unit, the first resistive bias unit configured to track the control output current;
a first bus coupled between the first switching unit and the first resistive bias unit, wherein the first control output signal is the voltage level between the first switching unit and first resistive bias unit;
a second switching unit coupled with the first current source, the second switching unit configured to switch based on a second control input signal;
a second resistive bias unit coupled with the second switching unit, the second resistive bias unit configured to track the control output current;
a second bus coupled between the second switching unit and the second resistive bias unit, wherein the second control output signal is the voltage level between the second switching unit and second resistive bias unit, wherein the first and second buses are coupled to a buffer unit configured to convert the first and second differential control output signals to a single-ended control output signal and the buffer unit is further configured to output the single-ended control output signal to a memory interface over a third bus.

4 more elements

A memory interface system, comprising:

a memory control hub configured to transfer data to a memory module by way of a buffer unit, the memory control hub comprising a control interface coupled to a first power supply and a common voltage supply, the control interface configured to drive a first and a second differential control output signal, wherein the voltage output swing of the first and second differential control output signals is between a differential voltage output level and the common voltage;
and
the memory module comprising a plurality of memory interfaces, each memory interface coupled to a second power supply, a common supply and the buffer unit, and each memory interface configured to drive a single-ended memory output signal to the buffer unit, wherein the single-ended memory output signal is driven to a voltage output high level to transfer a logic high, and the single-ended memory output signal is driven to the common supply voltage to transfer a logic low.

Dependencies are inferred from the claim text.

Differential memory interface system

Life of this patent

Differential memory interface system

Life of this patent

Abstract

Claims21