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US 6,747,479 B1Granted
Interface scheme for connecting a fixed circuitry block to a programmable logic core
AssigneeCypress Semiconductor Corporation
InventorsAlan J. Coppola, Joel Stanley, Steven J. E. Wilton
Life of this patent
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Abstract
An apparatus comprising one or more configurable interface tiles. The configurable interface tiles may be configured to communicate one or more signals between one or more programmable logic cores and one or more fixed function cores. The one or more configurable interface tiles, the one or more programmable logic cores and the one or more fixed function cores may be integrated on a single chip.
Claims20
An apparatus comprising:
- one or more configurable interface tiles configured to communicate one or more signals between a programmable logic core and a fixed function core, wherein said one or more configurable interface tiles, said programmable logic core and said fixed function core are integrated on a single chip and at least one of said one or more configurable interface tiles comprises a buffer section configured to present a signal as registered or unregistered.
A method for constructing a device comprising the steps of:
- (A) selecting one or more pre-defined fixed-function cores;
- (B) selecting one or more pre-defined programmable logic cores;
- (C) selecting a plurality of configurable interface tiles, wherein (i) a first configurable interface tile comprises a multiplexer part, (ii) a second configurable interface tile comprises a buffer part and (iii) said configurable interface tiles are configured to couple signals between said fixed-function cores and said programmable logic cores;
- and
- (D) integrating said one or more fixed function cores, said one or more programmable logic cores and said configurable interface tiles on a single chip.
2 more elements
An apparatus comprising:
- one or more configurable interface tiles configured to communicate one or more signals between a programmable logic core and a fixed function core, wherein said one or more configurable interface tiles, said programmable logic core and said fixed function core are integrated on a single chip and at least one of said one or more configurable interface tiles comprises a buffer section comprising a parallel-to-serial converter.
Dependencies are inferred from the claim text.