Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same

#This invention pertains to the field of microelectronics and, more particularly, to the field of fabricating and interconnecting extremely small semi-conductor devices commonly referred to as “chips.”

#The present invention is related to certain inventions assigned to the assignee of the present invention. These are in co-pending applications YOR920010217US1 and 20010216US1, the disclosures of which are cross-referenced and incorporated herein.

#Increased levels of integration in the silicon transistor technology over the last two decades have facilitated the migration from large scale integrated (LSI) to very large scale integrated (VLSI) and now to ultra-large scale integrated (ULSI) circuits for use in silicon chips for computing, communication and micro controller applications. Optimum utilization of these highly integrated silicon chips requires a more space efficient packaging with supporting devices such as memory chips. Further, with the advent of mobile communication devices, hand held organizers and computing devices, there has also been a push to integrate such varied functions into a single compact system. This in turn has led to the push in the microelectronics industry towards system-on-a-chip (SOC) approach.

#FIG. 1 illustrates a carrier with metal depositions over a contact receptacle that was formed in an earlier deposited dielectric film.

#FIG. 2 shows the carrier after removal of the metal, in the form of copper, from the surface by chemical mechanical polishing (CMP) and deposition of a nickel layer and Pd dendrites.

#FIG. 3 depicts the carrier after etching of the TaN—Ta layer above the dielectric, and showing temporary joining of a stud extending from a device chip.

#It will become apparent as description of the invention proceeds that because the aforenoted objects are fulfilled there is an ability, according to the invention, to test devices that have to be tested and “burned in” as a part of a collection of devices that form a functional system (e.g., electro/optical system, network switching systems, a multiprocessor parallel computing systems) thereby to ensure system level operability and performance. Consequently, this allows a selection of a group of chips that are known to be good as a group; alternately, the method of the invention allows a sorting of a particular part or chip that is prone to low yield or varying levels of performance by testing a number of chips mounted on the test carrier 10 along with a known good collection of other chips that make up the full system. When the testing is completed the temporarily attached device chips can be separated from the test carrier.

#It will be understood that when one begins the fabrication method in accordance with the present invention, one starts with the carrier component 10 constituted of the material 12, such as silicon, ceramic or organic carrier, with the interchip wiring 16. Wiring of contacts to connect to external electronics must be carried out. The wiring will have multiple levels and the carrier will also have vias, not shown on FIG. 1, but extending through the carrier 10 to allow for connections to the back of the carrier.

#It will be seen that the representative receptacle 20, as seen in FIG. 1, extends into the dielectric layer 14 where contacts to the device chips are made with respect to a representative device wafer 30 with a representative stud 32 extending from it and having a metal tip 39 (FIG. 3). The important point to note is that the size of the receptacles 20 can be as small as about 2.5 microns. The size of the receptacle, additionally, is about 20% larger than the size of the stud 32.