Method and apparatus to estimate burn-in time by measurement of scribe-line devices, with stacking devices, and with common pads

An apparatus for estimating burn-in tins for integrated circuits comprising:

• means for providing a substrate;
• means for forming a plurality of testing structures on said substrate, said means comprising:
• means for forming a plurality of evaluation device structures on said substrate, each device structure created to permit evaluation of failure mechanisms of said integrated circuit,
• means for forming a first forcing input pad to provide a first forcing stimulus to at least one of said evaluation device structures to provide a first stimulus to stress said evaluation device structure,
• means for forming a second forcing input pad to provide a second forcing stimulus to at least one of said evaluation device structures to provide a second stimulus to further stress said evaluation device structure,
• means for forming a first sensing output pad connected to sense first response from at least one of said evaluation device structures,
• means for forming a second sensing output pad connected to sense a second response from at least one of said evaluation device structures, and
• means for forming a selection circuit connected to selectively communicate the second stimulus to at least one selected evaluation device structure and the second response from the selected evaluation devices structure;
• means for activating said first and second stimuli;
• means for stressing said substrate;
• means for examining each selected evaluation device structure for failure;
• means for determining a hazard rate for each failure mechanism of said integrated circuit;
• and
• means for determining a burn-in time for said integrated circuit.

A reliability testing structure formed on a substrate comprising:

• a plurality of evaluation device structures formed on said substrate, each device structure created to permit evaluation of one of a plurality of failure mechanisms of said integrated circuit;
• a first forcing input pad to provide a first forcing stimulus to at least one of said evaluation device structures to provide a first stimulus to stress said evaluation device structure;
• a second forcing input pad to provide a second forcing stimulus to at least one of said evaluation device structures to provide a second stimulus to further stress said evaluation device structure;
• a first sensing output pad connected to sense first response from at least one of said evaluation device structures;
• a second sensing output pad connected to sense a second response from at least one of said evaluation device structures;
• and
• a selection circuit connected to selectively communicate the second stimulus to at least one selected evaluation device structure end the second response from the selected evaluation device structure.

A method for forming a reliability testing structure on a substrate comprising the steps of:

• providing a substrate;
• forming a plurality of testing structures on said substrate, each testing structure being formed by the steps of:
• forming a plurality of evaluation device structures on said substrate such that multiple evaluation device structures are placed on said substrate in a stack, each device structure created to permit evaluation of failure mechanisms of said integrated circuit and,
• forming a first forcing input pad to provide a first forcing stimulus to at least one of said evaluation device structures to provide a first stimulus to stress said valuation device structure,
• forming a second forcing input pad to provide a second forcing stimulus to at least one of said evaluation device structures to provide a second stimulus to further stress said evaluation device structure,
• forming a first sensing output pad connected to sense first response from at least one of said evaluation device structures,
• forming a second sensing output pad connected to sense a second response from at least one of said evaluation device structures, and
• forming a selection circuit connected to selectively communicate the second stimulus to at least one selected evaluation device structure and the second response from the selected evaluation devices structure.