Circuit for correcting deviation in oscillating frequency
AssigneeOki Electric Industry Co., Ltd.
InventorShinichi Kouzuma
Life of this patent
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Abstract
A frequency correction circuit for accurately correcting clock signals of an oscillating frequency with a simplified configuration without adjusting an oscillator circuit generating the oscillating frequency. A count adjuster of a time-base counter (TBC) receives a delay control signal and a clock signal. The count adjuster includes an inverter and an AND gate. The inverter is responsive to the delay control signal and develops an output signal, while the AND gate receives the clock signal. During the high level period of the delay control signal, the AND gate sends out the clock signal, from which one clock has been erased, as a clock signal of the initial stage T-type flip-flop of a clock frequency divider, which then produces an output signal, from which deviations have been removed.
Claims29
A frequency correction circuit for correcting a deviation in frequency of a signal generated from a clock signal obtained from an oscillator circuit, said oscillator circuit comprising an oscillator device for generating a reference clock signal, and first and second capacitive elements, each of the capacitive elements having one end connected across the oscillator device and another end grounded, said frequency correction circuit comprising:
- a clock frequency divider for frequency-dividing the clock signal into a desired frequency, said clock frequency divider comprising a plurality of counters connected in cascade, each of said plurality of counters frequency-dividing the clock signal and supplying a frequency-divided output to successive one of said plurality of counters as a clock;
- and
- a correction controller for controlling said clock frequency divider;
- said clock frequency divider further comprising a count adjuster for adjusting timing of counting carried out in response to the clock signal to cancel an error contained in the clock signal;
- said correction controller comprising:
- a time setting circuit for setting of first and second reference times and initializing said clock frequency divider;
- a time generator for calculating a generation time corresponding to a sum of the first reference time supplied from said time setting circuit and a time from said clock frequency divider;
- a time comparator for comparing the generation time with the second reference time;
- and
- a count controller operative in response to said time comparator for supplying said count adjuster with a control signal controlling said plurality of counters to delay or hasten a timing of counting.
Dependencies are inferred from the claim text.