Flip-chip packaging

A power semiconductor package comprising:

• a bottom mounting surface having at least one first terminal extending from said bottom mounting surface;
• at least one second terminal extending from said bottom mounting surface being co-planar with said first terminal;
• at least one third terminal extending from said bottom mounting surface being co-planar with said first terminal;
• a semiconductor power enhancement mode JFET die having a top surface defining a drain connection and a bottom surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, said top surface being coupled to an X-lead frame such that said first terminal is electrically connected to said drain;
• a first conductive region disposed on said mounting surface such that said second terminal is electrically connected to said source, and
• a second conductive region disposed on said mounting surface such that said third terminal is electrically connected to said gate.

A power semiconductor housing comprising:

• a power enhancement mode JFET die having a top surface defined as a drain, a first bottom surface region defined as a source and a second bottom surface region defined as a gate;
• an X-lead frame bonded to a first lead on a mounting surface and forming electrical coupling between said drain and said first lead by means of angular extensions of said X-lead frame contacting said drain;
• a second lead on said mounting surface contacting said first bottom surface region providing electrical coupling with said source;
• a third lead on said mounting surface contacting said second bottom surface region providing electrical coupling with said gate, and
• wherein said first lead, said second lead and said third lead are coplanar on said mounting surface.