Composite dielectric with improved etch selectivity for high voltage MEMS structures
AssigneeAnalog Devices, Inc.
InventorsThomas K. Nunan, David E. Grosjean, Denis M. O'Kane, James S. Sellars
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Abstract
A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.
Claims15
A semiconductor device, comprising:
- a substrate;
- and
- a semiconductor layer structure formed on the substrate, the semiconductor layer structure including at least one dielectric layer having a first border region and a second border region,
- wherein the dielectric layer exhibits increased etch selectivity characteristics at the first border region relative to the second border region, and exhibits increased electrical isolation characteristics at the second border region relative to the first border region, and
- wherein at least a portion of the dielectric layer is released from the substrate.
A semiconductor device, comprising:
- a substrate;
- and
- a semiconductor layer structure formed on the substrate, the semiconductor layer structure including at least one dielectric layer having a first border region and a second border region,
- wherein the dielectric layer exhibits increased etch selectivity characteristics at the first border region relative to the second border region, and exhibits increased electrical isolation characteristics at the second border region relative to the first border region,
- wherein the dielectric layer includes a composite stack of silicon nitride sub-layers providing successively reduced silicon content from the first border region toward the second border region,
- wherein the composite stack includes a silicon-rich nitride sub-layer at the first border region and a stoichiometric silicon nitride sub-layer at the second border region, and
- wherein the composite stack further includes at least one silicon nitride sub-layer disposed between the silicon-rich nitride sub-layer and the stoichiometric silicon nitride sub-layer.
A semiconductor device, comprising:
- a substrate;
- and
- a semiconductor layer structure formed on the substrate, the semiconductor layer structure including at least one dielectric layer having a first border region and a second border region,
- wherein the dielectric layer exhibits increased etch selectivity characteristics at the first border region relative to the second border region, and exhibits increased electrical isolation characteristics at the second border region relative to the first border region, and
- wherein the dielectric layer is configured as a trench lining dielectric.
Dependencies are inferred from the claim text.