Method and packaging structure for optimizing warpage of flip chip organic packages

#1. Field of the Invention

#The present invention relates to an electronic packaging structure constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

#In the current technology the utilization of flip chips which are mounted on an organic substrate of electronic packaging modules is subject to a tendency of the module components to warp at lower temperatures subsequent to cooling down from the cure temperature of an underfill between the components, and during temperature cycling of the modular package. This warpage of the components such as the chips and substrate, is caused by the considerable differences in the coefficients of thermal expansion (CTE) between the essentially silicon material of the chips, which may possess a CTE of 3 ppm/° C., and that of the circuitized chip carrier or substrate which is normally basically consistent of an organic material or laminate such as an epoxy, possessing a CTE of approximately 18 ppm/° C. Moreover, the encountered warpage is also increased as a result of the extensive mechanical coupling between the components which is introduced through the use of the underfill encapsulation. Moreover, the bending stiffness of respectively the chip, underfill encapsulant and of the organic material forming the chip carrier or substrate, is also of an important consideration in determining the potential warpage of the module.

#Reference may now be made to the following detailed description of a preferred embodiment of the invention, taken in conjunction with the accompanying drawings; in which:

#FIG. 1 illustrates a top plan view of a silicon chip which mounted on an organic substrate, wherein the chip is essentially in parallel relationship therewith as currently in the prior art;

#FIG. 2 illustrates a fragmentary sectional view taken along line 2—2 in FIG. 1, shown on a somewhat enlarged scale.

#Referring in specific detail to FIGS. 1 and 2 of the drawings, there is illustrated a modular package 10 comprising a silicon chip 12 of essentially a rectangular configuration which is positioned on a laminated substrate 14 comprising a flexible or laminated organic material, such as an epoxy or the like, and attached through the application of suitable solder joint array 16. Intermediate the chip 12 and the module 16 there is provided an underfill material 18 which is constituted of thermally curable adhesive.

#In view of the extreme differences in the coefficients of thermal expansion (CTEs) between the silicon chip 12 (3 ppm/° C.) and the organic chip carrier or substrate 14 (18 ppm/° C.), and due to the strong mechanical coupling between these components, introduced by the C4 solder points and encapsulation through the underfill material 18, and predicated on the inherent bending stiffnesses of the chip, underfill and organic carrier materials there is generated a thermal stress resulting in the various warpages of the respective package or module components which could cause delamination thereof and adversely affect the operability and reliability of the electronic package employing these components. Outside of the chip shadow, as shown in FIGS. 1 to 3 of the drawings, at the corner 22 of the substrate 14 or module which is designated as point A, pursuant to the prior art, point B which is a corner 24 of chip 12, and point C which is a C4 solder joint array corner 16, these are superimposed on each other and are aligned with point A. In contrast with the foregoing, pursuant to the invention as shown in FIG. 4, it is intended to rotate points B and C away from critical point A, inasmuch as this can reduce module warpage to an appreciable extent and optimize the stresses imposed on the most critical solder joints.

#In order to obviate or improve upon the foregoing arrangement so as to reduce module warpage and improve package reliability, as illustrated in FIG. 4 of the drawings, the chip 12 is rotated about the z axis relative to the organic carrier or substrate 14; preferably through an angle of about 45° whereby the chip corner 24 (point B), C4 solder joint array 16 (point C), which are superimposed on each other, as shown in FIG. 1 and 2, and the corner 22 (point A) of the laminate substrate 14 are now rotated and offset angularly relative to each other.