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US 6,747,326 B2Granted
Low voltage high performance semiconductor device having punch through prevention implants
AssigneeMicron Technology, Inc.
InventorLuan C. Tran
Life of this patent
Estimating the term…
Abstract
A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.
Claims24
A semiconductor device, comprising:
- a semiconductor substrate having an active region;
- a gate structure on said active region;
- at least one dummy gate spaced apart from said gate structure;
- source and drain regions adjacent to said gate structure, said source and drain regions being of a first conductivity type;
- a punch through prevention implant dopant of a second conductivity type below at least one of said source and drain regions, wherein said dopant forms a barrier between said at least one of said source and drain regions and the underlying substrate and wherein said barrier is graded such that the dopant concentration increases toward said gate structure, and decreases away from said gate structure toward the central region of each of said at least one of said source and drain regions.
2 more elements
A semiconductor device, comprising:
- a semiconductor substrate having an active region;
- a first structure on said active region, said first structure comprising a gate structure;
- source and drain regions adjacent to said gate structure, said source and drain regions being of a first conductivity type;
- a punch through prevention implant dopant of a second conductivity type below at least one of said source and drain regions, wherein said dopant forms a barrier between said at least one of said source and drain regions and the underlying substrate said barrier being substantially co-terminous with said at least one of said source and drain regions, and wherein said barrier varies in thickness such that the barrier thickness increases at the respective outer portions of each of said at least one of said source and drain regions relative to the barrier thickness at the corresponding central portion of each of said at least one of said source and drain regions.
1 more element
A low voltage, high speed semiconductor transistor device having low threshold voltage and reduced parasitic capacitance, comprising:
- a first structure over a substrate, the first structure comprising a gate structure;
- source and drain regions adjacent to and on either side of said gate structure;
- and
- a punch through prevention implant dopant of a second conductivity type forming a barrier between at least one of said source and drain regions and the underlying substrate, said barrier being graded such that the dopant concentration increases at the respective outer portions of each of said at least one of said source and drain regions relative to the dopant concentration at the corresponding central portion of each of said at least one of said source and drain regions.
1 more element
A semiconductor device, comprising:
- a semiconductor substrate having an active region;
- a first structure on said active region, said first structure comprising a gate structure;
- source and drain regions adjacent to said gate structure, said source and drain regions being of a first conductivity type;
- a punch through prevention implant dopant of a second conductivity type below at least one of said source and drain regions, wherein said dopant forms a barrier between said at least one of said source and drain regions and the underlying substrate, wherein said barrier varies in thickness such that the barrier thickness increases at the respective outer portions of each of said at least one of said source and drain regions relative to the barrier thickness at the corresponding central portion of each of said at least one of said source and drain regions, and wherein said barrier does not extend into a channel region under said gate structure.
1 more element
Dependencies are inferred from the claim text.