Method to form a self-aligned CMOS inverter using vertical device integration

A closely-spaced, vertical NMOS and PMOS transistor pair comprising:

• a substrate comprising silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers;
• a vertical NMOS transistor in said overlying silicon layer, said vertical NMOS transistor comprising:
• a drain overlying said oxide layer;
• a channel region overlying a part of said drain;
• a source overlying said channel region;
• a gate trench that exposes a top surface of said drain and a vertical surface of said channel region;
• and
• a gate comprising a polysilicon sidewall spacer
• adjacent to said vertical surface of said channel region with a gate oxide layer therebetween;
• and
• a vertical PMOS transistor in said overlying silicon layer, said PMOS transistor comprising:
• a drain overlying said oxide layer wherein said drain contacts said vertical NMOS transistor drain;
• a channel region overlying a part of said drain;
• a source overlying said channel region;
• and
• a gate trench that exposes a top surface of said drain and a vertical surface of said channel region;
• a gate comprising a polysilicon sidewall spacer adjacent to said vertical surface of said channel region with a gate oxide layer therebetween;
• an interlevel dielectric layer overlying said closely spaced, vertical NMOS and PMOS transistor pair, wherein said interlevel dielectric layer has openings that expose said PMOS source and drain and said NMOS source and drain;
• a metal silicide layer in said PMOS source and drain and said NMOS source and drain;
• and
• a patterned metal layer overlying said interlevel dielectric layer and said metal silicide layer.