Single poly EEPROM with reduced area
AssigneeTexas Instruments Incorporated
InventorsJozef C. Mitros, Lily Springer, Roland Bucksch
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Abstract
An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.
Claims14
A single polysilicon layer Electrically Erasable Programmable Read Only Memory CEEPROM) device comprising:
- a source region;
- a drain region;
- and
- a polysilicon layer further comprising:
- a floating gate comprising at least one polysilicon finger operatively coupling the source region and drain region;
- and
- a control gate comprising at least one polysilicon finger capacitively coupled to the floating gate.
An Electrically Erasable Programmable Read Only Memory (EEPROM) device comprising:
- a source region;
- a drain region;
- a polysilicon layer further comprising:
- a floating gate comprising at least one polysilicon finger operatively coupling the source region and drain region;
- a control gate comprising at least one polysilicon finger capacitively coupled to the floating gate wherein the control gate and floating gate fingers are substantially parallel to one another;
- and
- a field oxide layer underlying the polysilicon layer.
Dependencies are inferred from the claim text.