FeRAM having BLT ferroelectric layer and method for forming the same

A ferroelectric memory device, comprising:

• a semiconductor substrate;
• a transistor comprising a gate insulating layer, a gate electrode formed on the semiconductor substrate and a doped region formed in the semiconductor substrate at an end of the gate electrode;
• a plug engaging to the doped region of the transistor;
• a capacitor including a bottom electrode formed on the plug, a (BixLay)Ti3O12 ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer;
• and
• wherein an angle between a crystal direction on a side of the (BixLay)Ti3O12 ferroelectric layer and the bottom and top electrodes is about 90°.

A method for manufacturing ferroelectric memory device, comprising:

• a) forming a first conductive layer for a bottom electrode on a semiconductor substrate;
• b) forming a (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90;
• c) forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer;
• d) patterning the second conductive layer, the (BixLay)Ti3O12 ferroelectric layer and the first conductive layer, wherein the edge of the (BixLay)Ti3O12 ferroelectric layer is exposed;
• e) performing a thermal treatment to align a crystal direction on the side of the (BixLay)Ti3O12 ferroelectric layer, wherein an angle between a crystal direction and the bottom and top electrodes ranges is about 90°.