Liquid crystal display and method
AssigneeLG. Philips LCD Co., Ltd.
InventorKi-Hyun Lyu
Life of this patent
Estimating the term…
Abstract
The number of mask steps used to fabricate a TFT in an AMLCD is reduced. In particular, source and drain metallizations, as well as doped and undoped semiconductor layers are patterned at the same time, and the source and drain metallizations and the doped semiconductor layer are etched in a single etching step using an insulating passivation layer as a mask to form source and drain electrodes. Manufacturing costs can be reduced and the manufacturing yield can be improved.
Claims17
A method for manufacturing a semiconductor device comprising the steps of:
- depositing a first semiconductor layer on a substrate;
- depositing a second semiconductor layer on said first semiconductor layer;
- depositing a conductive layer on said second semiconductor layer;
- depositing a passivation layer on said conductive layer;
- patterning said passivation layer to provide a plurality of openings exposing said conductive layer;
- and
- etching portions of said conductive layer and said second semiconductor layer in a single processing step using said patterned passivation layer as a mask.
A method of fabricating a semiconductor device, comprising the steps of:
- forming a semiconductor layer on a surface of a substrate;
- forming a first conductive layer on said semiconductor layer;
- forming a passivation layer on said first conductive layer;
- patterning said passivation layer to provide first and second openings in said passivation layer to expose first and second portions, respectively, of said first conductive layer;
- forming a second conductive layer on said passivation layer and extending through said first opening to contact said first conductive layer;
- and
- etching said second portion of said first conductive layer and a portion of said semiconductor layer underlying said second portion of said conductive layer in a single processing step using said patterned passivation layer as a mask.
A method of manufacturing an active matrix liquid crystal display, comprising the steps of:
- depositing a first metal layer on a substrate;
- patterning said first metal layer to form a gate electrode;
- depositing a gate insulating layer on said substrate and said gate electrode;
- depositing a first semiconductor layer on said gate insulating layer;
- depositing an etch resistant layer on said first semiconductor layer;
- patterning said etch resistant layer to form an etch stop portion;
- depositing a second, impurity containing, semiconductor layer on said etch stop portion and said first semiconductor layer;
- depositing a second metal layer on said impurity containing layer;
- patterning said second metal layer;
- said second impurity containing semiconductor layer and said first semiconductor layer in a single step;
- depositing a passivation layer on said patterned second metal layer and said gate insulating layer;
- patterning said passivation layer to form an opening over said etch stop portion and a contact hole over part of said patterned second metal layer;
- depositing a transparent conductive layer on said patterned passivation layer and in said contact hole;
- patterning said transparent conductive layer to form a pixel electrode electrically connected to said part of said patterned second metal layer;
- and
- etching said second metal layer and said second impurity containing semiconductor layer in a single processing step using said patterned passivation layer as a mask to thereby form source and drain electrodes.
A method for manufacturing a semiconductor device comprising the steps of:
- depositing a first semiconductor layer on a substrate;
- depositing a second semiconductor layer on said first semiconductor layer;
- depositing a conductive layer on said second semiconductor layer;
- depositing a passivation layer on said conductive layer;
- patterning said passivation layer to provide a plurality of openings exposing said conductive layer;
- and
- etching portions of said conductive layer and said second semiconductor layer in a single processing step using said patterned passivation layer as a mask, whereby an etch stop portion is exposed through one of the plurality of openings.
Dependencies are inferred from the claim text.