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US 6,746,927 B2Granted
Semiconductor device having a polysilicon line structure with increased metal silicide portions and method for forming the polysilicon line structure of a semiconductor device
AssigneeAdvanced Micro Devices, Inc.
InventorsThorsten Kammler, Karsten Wieczorek, Christof Streck
Life of this patent
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Abstract
A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.
Claims36
A method, comprising:
- forming at least one feature of a silicon-containing semiconductive material on a substrate, said feature having sidewalls and an upper surface;
- forming a dielectric layer on said sidewalls of said at least one feature, said dielectric layer covering portions of said substrate adjacent said sidewalls;
- introducing dopant material into at least the portions of said substrate not covered by said feature and said dielectric layer on said sidewalls;
- removing said dielectric layer so as to expose the sidewalls of said feature;
- and
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming said spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one feature and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one feature are exposed.
3 more elements
A method of forming a gate electrode, the method comprising:
- forming at least one polysilicon line above an active region of a substrate;
- introducing a first dopant material into at least one portion of said active region not covered by said at least one polysilicon line and into said at least one polysilicon line;
- forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said active region adjacent to said sidewalls;
- introducing a second dopant material into at least the portions of the active region not covered by said polysilicon line and said dielectric layer, wherein introducing said second dopant material comprises implanting said second dopant material at a second predefined concentration and diffusing said dopant material during a second thermal treatment;
- removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line;
- and
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions.
4 more elements
A method, comprising:
- forming at least one polysilicon line above a substrate;
- introducing a first dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line;
- forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls;
- introducing a second dopant material at a second predefined concentration higher than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer, wherein introducing said second dopant material comprises implanting said dopant material at said second predefined concentration and diffusing said second dopant material during a second thermal treatment;
- removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line;
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions;
- and
- forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line.
5 more elements
A method, comprising:
- forming at least one polysilicon line above a substrate;
- introducing a first dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line;
- forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls;
- introducing a second dopant material at a second predefined concentration lower than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer, wherein introducing said second dopant material comprises implanting said second dopant material at said second predefined concentration and diffusing said dopant material during a second thermal treatment;
- removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line;
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions;
- and
- forming a metal suicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line.
5 more elements
A method of forming a gate electrode, the method comprising:
- forming at least one polysilicon line above an active region of a substrate;
- introducing a first dopant material into at least one portion of said active region not covered by said at least one polysilicon line and into said at least one polysilicon line;
- forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said active region adjacent to said sidewalls;
- introducing a second dopant material into at least the portions of the active region not covered by said polysilicon line and said dielectric layer;
- removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line;
- and
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed.
4 more elements
A method, comprising:
- forming at least one polysilicon line above a substrate;
- introducing a fist dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line;
- forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls;
- introducing a second dopant material at a second predefined concentration higher than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer;
- removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line;
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed;
- and
- forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line.
5 more elements
A method, comprising:
- forming at least one polysilicon line above a substrate;
- introducing a first dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line;
- forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls;
- introducing a second dopant material at a second predefined concentration lower than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer;
- removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line;
- forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed;
- and
- forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line.
5 more elements
Dependencies are inferred from the claim text.