Back to results
US 6,746,926 B1Granted
MOS transistor with highly localized super halo implant
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
Estimating the term…
Abstract
A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in the source/drain junction. The halo implant is performed through a gap formed by removal of a temporary spacer. The MOSFET is then further completed.
Claims10
A method of making a MOSFET, comprising:
- first providing a substrate having a gate oxide and gate thereon, the gate defining a channel region of no more than 50 nm length;
- second performing a source/drain extension implant;
- third forming a spacer on the gate;
- fourth performing epitaxy to form raised source/drain regions;
- fifth forming a silicide on the gate and source/drain regions;
- sixth removing the spacer, thereby forming a void region between the source/drain regions and the gate;
- seventh performing a halo implant through the void, thereby forming a halo around the gate in the channel region;
- and
- eighth completing the MOSFET.
6 more elements
A method of making a MOSFET, comprising:
- first providing a substrate having a gate oxide and gate thereon, the gate defining a channel region of no more than 50 nm length;
- second performing a vertical source/drain extension implant to a depth of approximately 10 nm to approximately 30 nm;
- thereafter forming a spacer on the gate;
- forming raised source/drain regions;
- forming a silicide on the gate and source/drain regions;
- removing the spacer, thereby forming a void region through the silicide between the source/drain regions and the gate;
- performing a halo implant through the void, thereby forming a halo around the gate in the channel region;
- and
- completing the MOSFET.
6 more elements
A method of making a MOSFET, comprising:
- providing a substrate having an isolation trench and a gate oxide and gate thereon, the gate defining a channel region of no more than 50 nm length;
- performing an approximately vertical source/drain extension implant in a region from the isolation trench to the gate, to a depth of approximately 10 nm to approximately 30 nm;
- forming a nitride spacer on the gate;
- performing epitaxy to form raised source/drain regions;
- forming a silicide on the gate and source/drain regions;
- removing the spacer, thereby forming a void region through the silicide between the source/drain regions and the gate;
- performing an approximately vertical halo implant to a depth of approximately 40 nm to approximately 100 nm, thereby forming a void region around the gate in the channel region;
- and
- completing the MOSFET.
6 more elements
Dependencies are inferred from the claim text.