A method of forming a DRAM memory, comprising the steps of:
- providing a semiconductor substrate of a first conductivity type;
- forming a shallow-trench-isolation (STI) structure having a plurality of parallel STI regions and a plurality of active regions formed alternatively on said semiconductor substrate, wherein each of the plurality of parallel STI regions is filled with a first raised field-oxide layer and each of the plurality of active regions comprises a first conductive layer being formed on a gate-dielectric layer;
- forming a second conductive layer, a capping-oxide layer, and a second masking dielectric layer sequentially over said STI structure to form a multilayer-gate structure;
- patterning said multilayer-gate structure using a plurality of masking photoresist (PR2) to define a plurality of transistor-stacks and a plurality of common-source and common-drain regions transversely to the plurality of active regions;
- removing sequentially said second masking dielectric layer, said capping-oxide layer, said second conductive layer outside of the plurality of masking photoresist PR2, etching selectively said first raised field-oxide layers to a depth equal to a thickness of said first conductive layer to form second raised field-oxide layers, removing selectively said first conductive layers, removing selectively said gate-dielectric layers and etching simultaneously said second raised field-oxide layers to form third raised field-oxide layers for forming a plurality of transistor-stacks, a first flat bed over each of the plurality of common-source regions, and a second flat bed over each of the plurality of common-drain regions, wherein said first/second flat beds are alternately formed by said semiconductor substrate in said active region and said third raised field-oxide layer in said parallel STI region;
- forming a buffer-dielectric layer over the plurality of transistor-stacks, said first flat beds, and said second flat beds and implanting doping impurities in a self-aligned manner across said buffer-dielectric layer into said semiconductor substrate of the plurality of active regions to form lightly-doped common-source and drain diffusion regions of a second conductivity type;
- forming a first sidewall dielectric spacer over a sidewall of said buffer-dielectric layer and implanting doping impurities in a self-aligned manner across said buffer-dielectric layer into said semiconductor substrate of the plurality of active regions to form heavily-doped common-source and drain diffusion regions of said second conductivity type within said lightly-doped common-source and drain diffusion regions;
- etching back selectively a thickness of said buffer-dielectric layer and simultaneously etching said first sidewall dielectric spacers to expose said first flat beds and said second flat beds outside of said first sidewall dielectric spacers;
- forming a planarized third conductive layer to fill up a gap between said first sidewall dielectric spacers and on said heavily-doped common-source/drain diffusion regions and said third raised field-oxide layers;
- etching back selectively said planarized third conductive layers in each of the plurality of common-source regions by using a non-critical masking photoresist step (PR3(a)-1) to form a thin third conductive layer over each of said first flat beds between said first sidewall dielectric spacers;
- forming a second sidewall dielectric spacer over a sidewall of said first sidewall dielectric spacers in each of the plurality of common-source regions and on a portion of said thin third conductive layer to define a source region for each of the plurality of transistor-stacks and simultaneously to define an isolation space between said source regions in each of the plurality of common-source regions;
- removing selectively said thin third conductive layer between said second sidewall dielectric spacers and etching anisotropically said semiconductor substrate in a self-aligned manner to form a plurality of self-aligned shallow trenches between said second sidewall dielectric spacers;
- forming a first planarized dielectric layer between said second sidewall dielectric spacers to simultaneously fill up each of the plurality of self-aligned shallow trenches;
- removing selectively said planarized third conductive layers, said second sidewall dielectric spacers, and said thin third conductive layers outside of the plurality of active regions by using a photo-mask for forming said STI structure to form planarized third conductive islands, second sidewall dielectric-spacer islands, and thin third conductive islands;
- forming second planarized dielectric layers to fill up gaps outside of the plurality of active regions for forming a DRAM transistor structure;
- and
- forming a DRAM capacitor structure over said DRAM transistor structure, wherein a rectangular tube-shaped cavity is formed over each of said thin third conductive islands for forming a DRAM capacitor and a planarized conductive contact-plug or a planarized conductive contact-island is formed over each of said planarized third conductive islands to act as a bit-line node for forming a plurality of bit lines being connected with said planarized conductive contact-plugs or said planarized conductive contact-islands.