Method of fabricating self-aligned cross-point memory array

A method of fabricating a self-aligned cross-point memory array having a partially aligned PCMO resistor pillar, comprising:

• preparing a substrate, including forming any supporting electronic structures;
• forming a p-well area on the substrate;
• implanting ions to form a deep N+ region;
• implanting ions to form a shallow P+ region on the N+ region to form a single, overlaying P+/N junction on the substrate;
• depositing a barrier metal layer on the P+ region;
• depositing a bottom electrode layer on the barrier metal layer;
• depositing a sacrificial layer on the bottom electrode layer, which includes depositing a layer of material taken from the group of materials consisting of polysilicon and silicon nitride;
• patterning and etching to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench;
• depositing oxide to fill the trench, thereby forming plural P+/N junctions;
• patterning and etching to remove portions of the sacrificial layer;
• depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer;
• depositing top electrode layer;
• patterning and etching the top electrode layer;
• and
• completing the self-aligned, cross-point memory array.

A method of fabricating a self-aligned cross-point memory array, comprising:

• preparing a substrate, including a forming supporting electronic structures;
• forming a p-well area on the substrate;
• implanting ions to form a deep N+ region, including implanting phosphorus ions at an energy of between about 60 keV to 200 keV and an ion dose of between about 5·1014 ions/cm−2 to 2·1015 ions/cm−2;
• implanting ions to form a shallow P+ region on the N+ region to form a P+/N junction, including implanting BF2 ions at an energy level of between about 20 keV to 60 keV and a dose of between about 1·1015 ions/cm−2 to 5·1015 ions/cm−2;
• depositing a barrier metal layer on the P+ region, including depositing a layer having a thickness of between about 10 nm to 50 nm of a barrier metal taken from the group of barrier metals consisting of TaN, TiN, WN, and TiTaN;
• depositing a bottom electrode layer on the barrier metal layer, including depositing a layer having a thickness of between about 50 nm to 300 nm of bottom electrode material taken from the group of electrode materials consisting of Pt and Ir;
• depositing a sacrificial layer on the bottom electrode layer, including depositing a layer of material taken from the group of materials consisting of polysilicon and silicon nitride, having a thickness of between about 200 nm to 400 nm;
• patterning and etching to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench;
• depositing oxide to fill the trench;
• patterning and etching to remove portions of the sacrificial layer;
• depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer;
• depositing a top electrode layer;
• patterning and etching the top electrode layer;
• and completing the self-aligned, cross-point memory array.