Transistor, semiconductor device and manufacturing method of semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorAkira Nishiyama
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorAkira Nishiyama
Estimating the term…
A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.
A method of manufacturing a semiconductor device comprising:
The method of manufacturing a semiconductor device comprising;
A method of manufacturing a semiconductor device comprising:
A method of manufacturing a semiconductor device comprising:
The method according to the 10, wherein upon depositing the second semiconductor layers of the first and second conductivity types, a field effect transistor formation region of either one of an n-type field effect transistor and a p-type field effect transistor is covered with a film containing nitride.
Dependencies are inferred from the claim text.