Thin film transistor and manufacturing process therefor

Abstract

An object of this invention is to provide a manufacturing process and structure of a thin film transistor having high productivity in which the resistance of a gate electrode wiring line can be decreased, an active layer and source and drain electrodes form an ohmic contact, and the number of masks required in the manufacturing process can be decreased. An amorphous silicon layer and a 1-st gate dielectric layer are consecutively deposited on an insulating substrate by plasma CVD. The 1-st gate dielectric layer is processed together with the amorphous silicon layer into an island shape. A 2-nd gate dielectric layer and a metal interconnection layer are deposited on the 1-st gate dielectric layer. After the metal interconnection layer is etched to form a gate electrode, the 2-nd and 1-st gate dielectric layers are etched to pattern the gate dielectric layer. Using the gate electrode as a mask, ion doping and laser irradiation are performed for the portion, of the amorphous silicon layer, that was exposed in the previous step. This portion is poly-crystallized to form source and drain regions.

Dependencies are inferred from the claim text.