Integrated chip package structure using silicon substrate and method of manufacturing the same

A chip packaging method comprising:

• providing a first substrate with a first surface;
• providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface;
• mounting the dies over the first surface of the first substrate, the active surfaces of the dies facing the first surface of the first substrate;
• thinning the dies from the backside;
• providing a second substrate with a second surface;
• mounting a second substrate over the backsides of the dies, the second surface of the second substrate facing the backsides of the dies;
• removing the first substrate;
• allocating a first dielectric layer over the second surface of the second substrate and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies;
• and
• allocating a first patterned wiring layer on the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes.